Kasemsuwan, Varakorn

Preferred name

Alternative Name

Kasemsuwan, V.

Kasemsuwan, Varakom

Main Affiliation

School of Engineering

varakorn.ka@kmitl.ac.th

Now showing 1 - 10 of 27

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A robust high-speed low input impedance CMOS current comparator
(2008-12-01)
Kasemsuwan, Varakorn
;
Khucharoensin, Surachet
In this paper, a robust high-speed low input impedance CMOS current comparator is proposed. The front end of the comparator uses the modified Wilson current-mirror and diode-connected transistors to perform a current subtraction and current to voltage conversion simultaneously. The circuit is immune to the process variation and has low input impedances. HSPICE is used to verify the circuit performance with a 0.5 μm CMOS technology. The simulation results show the propagation delay of 1.67 ns, input impedances of 123 Ω, and 126 Ω, and average power dissipation of 0.63 mW for ± 0.1 μA input current under the supply voltage of 3 V. © 2008 World Scientific Publishing Company.
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An analytical transit time model for short channel MOSFET's
(2000-12-01)
Kasemsuwan, Varakorn
An analytical transit time model for short channel MOSFET is presented. Several second order effects such as short channel and narrow width effects, mobility degradation, parasitic drain and source resistance, velocity saturation and channel length modulation are included in the model. The model shows good agreements with the experimental and two dimensional numerical data over a wide range of biasing conditions. © 2000 IEEE.
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A 3Volt high frequency and low input impedance CMOS current-mode precision full-wave rectifier
(2002-12-01)
Khucharoensin, Surachet
;
Kasemsuwan, Varakorn
This paper presents a 3Volt high frequency and low input impedance CMOS current mode precision full-wave rectifier. The circuit is designed based on an improved Wilson current miller. All MOS transistors are biased at low current resulting in small power dissipation. Negative feedback has been employed to reduce the input impedance of the circuit(236Ω). HSPICE is used to perform the simulation and the result shows the frequency of operation as high as 100 MHz with a standard 0.5μm CMOS technology. The mismatch obtained from the input and rectifier's output is 0.21% for an input current of ±150μA. The DC transfer characteristic shows good linearity, very sharp corner at zero crossing point and good symmetry during positive and negative input cycle while power dissipation is 5.8μW. © 2002 IEEE.
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An analytical model of short channel MOSFET including velocity overshoot
(2002-01-01)
Kasemsuwan, V.
In this paper, an analytical model of short channel MOSFET including velocity overshoot is proposed. The model is developed based on the solution of energy balance equation under the assumption of displaced Maxwellian distribution. The resulting model is the augmented drift-diffusion velocity model. The parameters involved in the velocity model are physical parameters with only one fitting parameter. The model also includes the effects of the mobility degradation, drain induced barrier lowering effect, source drain series resistance and the channel length modulation. The theoretical predictions of the model are compared with the experimental data and shown to be in good agreement over a wide range of bias conditions. © 2002 IEEE.
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A physics-based model of short channel MOSFET including velocity overshoot
(2002-12-01)
Kasemsuwan, Varakom
This paper presents a physics-based modeling of short channel MOSFET including velocity overshoot. The model is developed based on the solution of energy balance equation under the assumption of drifted Maxwellian distribution. Electron temperature is analytically obtained along the channel and the thermoelectric current is then derived. The model includes the effects of the mobility degradation, channel length modulation, drain induced barrier lowering and parasitic drain source resistance. The theoretical predictions of the model are compared with the experimental data and shown to be in good agreement over a wide range of bias conditions. © 2002 IEEE.
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A 1 volt CMOS pseudo differential amplifier
(2006-01-01)
Suadet, Apirak
;
Kasemsuwan, Varakorn
This paper presents a 1 V CMOS pseudo differential amplifier using simple rail-to-rail CMFB circuit. The proposed circuit employs the complementary common mode feedback (CMFB) consisting of common mode detector, transimpedance and transconductance amplifiers. The simulation results using HSPICE under a 0.18 μm CMOS technology shows that the rail to rail output swing is achieved with low common mode gain (-36 dB). The differential output swing of the circuit is ± 0.7 V. The power dissipation of the circuit is 0.23 mW. © 2006 IEEE.
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Current-mode pseudo-exponential-control variable-gain amplifier using fourth-order Taylor's series approximation
(2006-03-30)
Arthansiri, T.
;
Kasemsuwan, V.
A new current-mode pseudo exponential-control variable-gain amplifier (VGA) using CMOS technology is proposed. The technique is based on the fourth-order Taylor's series approximation. The VGA exhibits a linear-dB controllable output range of 30 dB with maximum error less than 0.5 dB.
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±1.5V high performance CMOS rail to rail voltage follower
(2002-01-01)
Kasemsuwan, V.
;
Boonyaporn, P.
;
Thanachayanont, A.
A ±1.5 V high performance CMOS rail to rail voltage follower is presented. The circuit is based on the symmetrical class AB voltage follower and can operate under supply voltages of 1.5 V. The proposed circuit has power dissipation of 5.2 mW under quiescent condition and can drive ±1.25 V to 250 Ω load with a total harmonic distortion of less than 0.5 percent and cut-off frequency of 237 MHz. Although simple, the proposed circuit enables the output transistors to drive the load efficiently.
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A high performance class AB CMOS rail to rail voltage follower
(2002-01-01)
Boonyaporn, P.
;
Kasemsuwan, V.
A high performance class AB CMOS rail to rail voltage follower is presented. The circuit is based on the symmetrical class AB voltage follower and can operate under supply voltages of ±1.5 V. The proposed circuit has power dissipation of 2.5 mW under quiescent condition and can drive ±1.2 V to 250 Ω load with a total harmonic distortion of less than 0.6 percent and cut off frequency of 131 MHz. Although simple, the proposed circuit enables the output transistors to drive loads efficiently.
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A 3V robust high-speed low input impedance CMOS current comparator
(2004-12-01)
Khucharoensin, Surachet
;
Kasemsuwan, Varakorn
In this paper, a 3V robust high speed low input impedance CMOS current comparator is proposed. The circuit uses modified Wilson current-mirror to perform a current subtraction. Negative feedback is employed to reduce input impedances of the circuit. The diode connected transistors of the same type(NMOS) are used at the output making the circuit immune to the process variation. HSPICE is used to verify the circuit performance and the results show the propagation delay of 1.67 nsec with an average power dissipation of 0.63 mW using a standard 0.5μm CMOS technology for an input current of ±0.1μA at the supply voltage of 3V. The input impedances of the proposed current comparator are 123 Ω and 126 Ω while the maximum output voltage variation is only 1.9%. ©2004 IEEE.

Kasemsuwan, Varakorn

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