Kasemsuwan, Varakorn

Preferred name

Alternative Name

Kasemsuwan, V.

Kasemsuwan, Varakom

Main Affiliation

School of Engineering

varakorn.ka@kmitl.ac.th

Now showing 1 - 10 of 25

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Low-voltage bulk-driven QFG-regulated self-cascode super MOS transistor
(2016-09-06)
Thongleam, Thawatchai
;
Suadet, Apirak
;
Kasemsuwan, Varakorn
A bulk-driven super MOS transistor (BD-SMT) for low voltage operation is presented. The proposed transistor achieves a high effective transconductance (G<inf>m(eff)</inf>), high effective drain impedance (R<inf>D(eff)</inf>) and low effective source impedance (R<inf>S(eff)</inf>). BD-SMT is designed based on regulated self-cascode and negative feedback techniques. The transistor been designed using a 0.18 μm CMOS technology and operated from a 0.4 V supply with a static power consumption of 12 μW. The simulation results showed higher G<inf>m(eff)</inf>, larger R<inf>D(eff)</inf> and smaller R<inf>S(eff)</inf> as compared to those of simple bulk-driven MOS transistor.
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A current-mode common-mode feedback circuit (CMFB) with rail-to-rail operation
(2011-06-13)
Suadet, Apirak
;
Kasemsuwan, Varakorn
This paper presents a current-mode commonmode feedback (CMFB) circuit with rail-to-rail operation. The CMFB is a stand-alone circuit, which can be connected to any low voltage transconductor without changing or upsetting the existing circuit. The proposed CMFB employs current mirrors, operating as common-mode detector and current amplifier to enhance the loop gain of the CMFB. The circuit employs positive feedback to enhance the output impedance and gain. The circuit has been designed using a 0.18 μm CMOS technology under 1 V supply and analyzed using HSPICE with BSIM3V3 device models. A pseudodifferential amplifier using two common sources and the proposed CMFB shows rail to rail output swing (± 0.7 V) with low common-mode gain (-36 dB) and power dissipation of 390 μW. Copyright © 2011 De Gruyter.
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A 0.5 volt rail-to-rail CMOS pseudo-differential OTA using simple feed-forward technique
(2011-08-12)
Suadet, Apirak
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Thongleam, Thawatchai
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Kasemsuwan, Varakorn
;
Vichienchom, Kasin
This paper presents a low voltage CMOS pseudo differential OTA using simple feed-forward technique. The circuit employs feed-forward technique to suppress the common-mode gain, and positive feedback to enhance the output impedance. The circuit is designed using 0.18 μm CMOS technology under 0.5 V supply. The simulation results show rail-to-rail input/output swing, achieved with low common-mode gain (-35 dB). The output swing of the circuit is 0.3 Vpp. The power dissipation of the circuit is 50 μW. © 2011 IEEE.
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Low voltage adjustable CMOS Schmitt trigger
(2011-07-01)
Singhanath, Pratchayaporn
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Suadet, Apirak
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Kanjanop, Arnon
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Thongleam, Thawatchai
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Kuankid, Sanya
This paper presents a low voltage adjustable CMOS Schmitt trigger using dynamic threshold MOS (DTMOS). Cross-coupled inverter with body control is employed to speed up the switching process, and control the intensity of the feedback. The proposed Schmitt trigger has been designed using 0.18 m 0.4 V CMOS technology and analyzed using PSPICE with BSIM3V3 device models. The simulation results show rail-to-rail operation and independently adjustable switching voltages for both low-to-high (V<inf>T(LH)</inf>) and high-to-low (V <inf>T(HL)</inf>) as high as 15 % of the supply voltage. The power dissipation is 0.13 W. © 2011 IEEE.
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A CMOS inverter-based class-AB pseudo differential amplifier for HF applications
(2010-12-01)
Suadet, Apirak
;
Kasemsuwan, Varakorn
This paper presents a CMOS inverter-based class-AB pseudo differential amplifier for HF applications using new simple rail-to-rail CMFB circuit. The proposed circuit employs two CMOS inverters and the complementary common-mode feedback (CMFB) consisting of current mode common-mode detector and transimpedance amplifiers. The circuit has been designed using 0.18 μm CMOS technology under 1 V supply, and the simulation results shows that the rail to rail output swing is achieved with low common-mode gain (-15 dB). The output swing of the circuit is 0.7 V. The power dissipation of the circuit is 96 μW. © 2010 IEEE.
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Feedforward bulk-driven class AB fully-differential second-generation current conveyor (FDCCII)
(2014-01-01)
Thongleam, Thawatchai
;
Kasemsuwan, Varakorn
In this paper, a feedforward bulk-driven class AB fully-differential second-generation current conveyer (FDCCII) is presented. Bulk-driven differential pair is employed for the input stage allowing the FDCCII to operate with rail-to-rail operation. Feedfoward technique is also incorporated into input stage to increase the DC gain and minimize the common mode gain. The circuit performance is verified using HSPICE in 0.18 μm CMOS technology. The simulation results show rail-to-rail input and output swings. The DC voltage transfer characteristic between ports Y and X and DC current transfer characteristic between ports X and Z shows good linearity. The bandwidths show 25.7 MHz (V<inf>X</inf>/V<inf>Y</inf>), 30 MHz (I<inf>Z</inf>/I<inf>X</inf>), respectively. The power dissipation is 267.5 μW. © (2014) Trans Tech Publications, Switzerland.
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A high-gain fully-differential thermal noise-canceling CMOS front-end amplifier
(2011-12-05)
Chimpleekul, Puttachai
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Kasemsuwan, Varakorn
This paper presents a fully-differential CMOS front-end amplifier using g<inf>m</inf>-boosting and noise-canceling techniques. The proposed front-end amplifier is designed based on a 0.18 μm standard CMOS process and 2 V supply. Simulation results show noise figure (NF) of 2.9 dB, while the voltage gain and bandwidth of the amplifier are 31.6 dB and 2 GHz, respectively. The power dissipation is 19 mW. © 2011 IEEE.
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A 0.7 V DTMOS-based class AB current mirror
(2011-12-05)
Kanjanop, Arnon
;
Kasemsuwan, Varakorn
A 0.7 V DTMOS-Based class AB current mirror is presented. The circuit is developed based on a conventional class AB current mirror structure with a common-source output stage. The circuit is designed using a 0.13 μm CMOS technology and operates under a 0.7 V supply. SPICE with BSIM3V3 model parameters is used to verify the circuit performance. The maximum current transfer is found to be 7 times larger than the input bias current, while the DC current gain is -0.03 dB. The bandwidth and power dissipation are 540 MHz and 96 μW, respectively. © 2011 IEEE.
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A 0.5 V quasi-floating gate self-cascode DTMOS current-mode precision full-wave rectifier
(2012-10-02)
Mitwong, Hanphon
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Kasemsuwan, Varakorn
This paper presents a 0.5 V quasi-floating gate self-cascode DTMOS current-mode precision full-wave rectifiers (PFWR). The circuit is designed based on improved Wilson current mirrors. All MOS transistors are biased on the edge of conduction, enabling the circuit to operate at low voltage with low power consumption. Negative feedback mechanism of the Wilson current mirror and cross coupling techniques have been employed to reduce the input impedance. Spectre is used to perform the simulation and the results show the frequency of operation as high as 100 MHz using a standard 0.13 μm CMOS technology. The mismatch between the input and rectifier's output is 0.24% for an input current of ±100 μA. The DC transfer characteristic shows good linearity, very sharp corner at zero crossing point and good symmetry during positive and negative input cycle, while power dissipation is 570 nW © 2012 IEEE.
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A 0.8 V quasi-floating-gate fully differential CMOS op-amp with positive feedback
(2011-08-12)
Thongleam, Thawatchai
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Suadet, Apirak
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Kasemsuwan, Varakorn
This paper presents a 0.8 V fully differential CMOS op-amp. The input stage of the circuit is designed using quasi-floating-gate (QFG) transistors with positive feedback, while QFG transistors in the output stage are connected in the class AB configuration. QFG transistors are employed, enabling the circuit to operate under low supply voltage. The proposed amplifier is designed using 0.18 μm CMOS technology, and simulation results show rail-to-rail input and output swings. The open-loop gain is 80.4 dB with the gain-bandwidth product of 8.66 MHz. Phase margin is 45° (C<inf>L</inf>= 20 pF). The CMRR is 107 dB (at 1 kHz) and the power consumption is 54.9 μW. © 2011 IEEE.

Kasemsuwan, Varakorn

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