Kasemsuwan, Varakorn

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Kasemsuwan, Varakorn
Alternative Name
Kasemsuwan, V.
Kasemsuwan, Varakom
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Email
varakorn.ka@kmitl.ac.th

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    Low-voltage bulk-driven QFG-regulated self-cascode super MOS transistor
    (2016-09-06)
    Thongleam, Thawatchai
    ;
    Suadet, Apirak
    ;
    Kasemsuwan, Varakorn
    A bulk-driven super MOS transistor (BD-SMT) for low voltage operation is presented. The proposed transistor achieves a high effective transconductance (G<inf>m(eff)</inf>), high effective drain impedance (R<inf>D(eff)</inf>) and low effective source impedance (R<inf>S(eff)</inf>). BD-SMT is designed based on regulated self-cascode and negative feedback techniques. The transistor been designed using a 0.18 μm CMOS technology and operated from a 0.4 V supply with a static power consumption of 12 μW. The simulation results showed higher G<inf>m(eff)</inf>, larger R<inf>D(eff)</inf> and smaller R<inf>S(eff)</inf> as compared to those of simple bulk-driven MOS transistor.
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    A 0.5 V quasi-floating gate self-cascode DTMOS current-mode precision full-wave rectifier
    (2012-10-02)
    Mitwong, Hanphon
    ;
    Kasemsuwan, Varakorn
    This paper presents a 0.5 V quasi-floating gate self-cascode DTMOS current-mode precision full-wave rectifiers (PFWR). The circuit is designed based on improved Wilson current mirrors. All MOS transistors are biased on the edge of conduction, enabling the circuit to operate at low voltage with low power consumption. Negative feedback mechanism of the Wilson current mirror and cross coupling techniques have been employed to reduce the input impedance. Spectre is used to perform the simulation and the results show the frequency of operation as high as 100 MHz using a standard 0.13 μm CMOS technology. The mismatch between the input and rectifier's output is 0.24% for an input current of ±100 μA. The DC transfer characteristic shows good linearity, very sharp corner at zero crossing point and good symmetry during positive and negative input cycle, while power dissipation is 570 nW © 2012 IEEE.
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    Low-voltage low-power current-mode amplitude shift keying (ASK) demodulator
    (2012-12-01)
    Mitwong, Hanphon
    ;
    Kasemsuwan, Varakorn
    A low-voltage low-power amplitude shift keying (ASK) demodulator using UMC 0.13 μm CMOS technology for wireless sensor network is presented. The circuit is developed based on a current-mode precision full wave rectifier, envelop detector, phase inverter and Schmitt trigger using dynamic threshold voltage MOS (DTMOS) transistor, quasi floating gate and self-cascode techniques. The circuit can operate at 0.5 V supply voltage at 2 Mbps with the power dissipation of 55 μW. © 2012 IEEE.
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    Low-voltage current-mode preamplifier based Latch comparator
    (2016-09-06)
    Jankatkit, Thongchai
    ;
    Kasemsuwan, Varakorn
    This paper presents a low-voltage latch current comparator. The circuit was designed on the basis of current mirror, preamplifier and latch circuits and also various circuit techniques; quasi-floating gate to reduce the input impedance, bulk driven technique for the circuit to be operable under low supply voltage and positive feedback to increase the gain and the overall speed. From the simulation results, which were presented with 0.18 um CMOS technology, the circuit can operate well at the supply voltage of 0.5 volt and the resulting propagation delay time were 2.2 nS and 1.4 nS when the input current differences are 1 uA and 10 uA, respectively. The total power dissipation was 79 uW.
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    A low-voltage low-power current-mode differential adjustable Schmitt trigger
    (2012-10-02)
    Tamnupan, Wuttipong
    ;
    Kasemsuwan, Varakorn
    This paper presents a low-voltage low-power current-mode differential adjustable Schmitt trigger. The proposed Schmitt trigger consists of current subtractor, current Schmitt trigger and voltage to current converter. The operation range is extended to all four quadrants of the input-output plane. Schmitt trigger is designed using UMC 0.13 μm CMOS technology and operates under the supply voltage of 0.7 V. The simulation results show that the hysteresis lie in the all quadrant of the input-output plane and the power dissipation is only 66 μW. © 2012 IEEE.