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Optical Absorption and Bandgap Modulation in Diamond-Like Carbon Films for Anti-Reflection
(2026-01-01)
Srisantirut, Tanawit
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Pengchan, Weera
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Phetchakul, Toempong
Diamond-like carbon (DLC) films were deposited onto glass and silicon substrates utilizing Electron Cyclotron Resonance Chemical Vapor Deposition (ECR-CVD) with an Argon/Acetylene gas mixture. Substrate biases were varied (0V,-55V,-100V) for both nitrogen-doped and undoped films. Optical band gap (Eg) decreased with increasing negative substrate bias specifically from 2.6 eV to 2.2 eV for nitrogen-doped DLC and from 1.6 eV to 1.3 eV for undoped DLC. Nitrogen doping generally results in films with wider band gaps compared to undoped films at equivalent biases to sp hybrid bond formation increasing bias reduces the band gap within each film type. I-V measurements revealed an increase in open-circuit voltage from approximately 0.648 V to a range of 0.678–0.698 V for cells incorporating nitrogen-doped DLC. This improvement is attributed to enhanced corrosion resistance and electrical conductivity suggesting the suitability of nitrogen-doped DLC for photovoltaic applications.
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Three-Phase Oscillator with Cascade Ability Using Voltage Current Conveyor
(2024-01-01)
Buakaew, Seangrawee
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Narksarp, Wipavan
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Choeysombat, Kamonthip
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Kanjanawiwin, Juthamas
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Atiwongsangthong, Narin
This paper presents a new circuit configuration employing voltage current conveyors (VCII) in conjunction with a minimal number of passive elements to achieve a voltage mode sinusoidal oscillator with a 3 -phase differential output. The proposed circuit features a straightforward architecture, with all passive elements connected to low-impedance nodes. Consisting solely of identical VCIIs without multiple outputs, the circuit facilitates the cascading of the 3 -phase outputs without requiring supplementary buffering. Simulation results obtained through PSPICE, along with experimental validation using commercial ICs, are provided to substantiate the efficacy of the proposed circuit.
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Diamond-like Carbon Thin Film Coating for Application on Heterojunction Solar Cells by ECR-CVD System
(2020-05-27)
Srisantirut, Tanawit
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Pengchan, Weera
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Phetchakul, Toempong
Diamond-like Carbon (DLC) film has the ability to change the refractive index value achieved high transmittance for potential applications of antireflection coating. DLC films were deposited on heterojunction solar cells by the ECR-CVD (Electron Cyclotron Resonance Chemical Vapor Deposition) method using Acetylene (C<inf>2</inf>H<inf>2</inf>) and Argon (Ar) gases. DLC coating affects ITO (Indium tin oxide), causing the electrical and resistivity of heterojunction solar cell vary according to the coating time. The surface and thickness of the DLC films was measured with an atomic force microscope. Illuminated I-V characteristic was investigated by photo-I-V measurements. The suitable acetylene anti-reflection deposition time at 0.40 minutes. Therefore, heterojunction solar cell was fabricated on a substrate using the optimized DLC films as an anti-reflection coating and it obtained an increase efficiency of about 1%.
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Optical and electrical properties of diamond-like carbon thin film with deposition by ecr-cvd system
(2019-01-01)
Srisantirut, Tanawit
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Pengchan, Weera
In this paper, evolution of optical and electrical properties of diamond-like carbon (DLC) films deposited by ECR-CVD system are reported. By varying the deposition different substrates bias (0,-55,-100 V) and volume amount of C2H2 from 40 to 55 cc onto substrate Si/TiN and quarts. The structure of the DLC films were analyzed from Raman spectroscopy. DLC films deposited bias at-100 V and C2H2 at 40 cc show excellent optical transmittance and high resistivity. As a result, ID/IG ratio corresponds to the optical transmittance and resistivity with ID/IG ratio decreased making the film like to the diamond. Most importantly, the transparency and resistivity properties of the DLC films can be tailored to approaching diamond by adjusting substrates bias and volume C2H2, is important to many applications, which is improve film properties.
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Effect of temperature on 16 nm n-FiNFET
(2018-01-01)
Pengchan, Weera
This research presents the effect of temperature that influence to the performance of 16 nm SOI n-FinFET structure. The structure has created with structure tool on GTS Framework. The transistor has 1 nanometer HfO<inf>2</inf> gate oxide with all metal contact and biased on Minimos-NT tool, with variation of temperatures from 300 K to 420 K with 30 K per step. The result found the decrease in saturation current, threshold voltage and mobility. The temperature brought electron and rose the density of electron as the potential from power supply that energized to the structure. They made mobility fall with them rising. The temperature makes a performance of FinFET structure.
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The influence of gate scaling to electrical characteristics on n-MOS FinFET
(2017-05-31)
Patchrasardtra, Nuttapong
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Pengchan, Weera
This paper investigates effects from gate scaling in Tri-gate FinFET structure by simulation method, to avoid problems and improve a structure to be good prototype. The experiments used GTS framework for simulation. Start from 20 nm device, then scaling to 22 nm 28 nm and 32 nm. Therefrom Minimos-NT function has used for biasing to giving two electrical characteristics as the drain current saturation and the threshold voltage. From these consequences can offer the subthreshold swing and the drain-induced barrier lowering by calculation. The results found that threshold voltage inversely proportional to saturated drain current, the subthreshold swing and the drain-induced barrier lowering. The short channel effect has affected to 20 nm model by highest DIBL. Therefore should be adjust the gate length and the oxide thickness properly to improve this effect.
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Influence of Temperature to Electron Mobility on Top of Channel in 14 nm n-FinFET
(2017-01-01)
Patcharasardtra, Nuttapong
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Pengchan, Weera
he temperature behavior that influential to the electron mobility on top surface in 14 nanometer FinFET channel. The Mobility could find on I-V characterizing simulation process and giving the result from the TCAD software by biasing on the FinFET structure with gate voltage at 1 volt and the drain-source voltage from 0 Volt to 1 Volt to obtain the saturation drain current from I-V characteristic. The Electron mobility was lowering by increasing the temperature from 303K (30°C) to 353K (80°C). This FinFET structure gave the I<inf>DS (Sat)</inf> about 29 µA and gave mobility at V<inf>DS</inf> = 0 Volt about 575 cm<sup>2</sup>/Vs, at V<inf>DS</inf> = 1 Volt, the mobility dramatically down to 3.4 cm<sup>2</sup>/Vs.
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Electrical characteristics of different gate geometry of FinFET
(2016-01-01)
Patcharasardtra, Nuttapong
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Pengchan, Weera
This paper proposed to the electrical characteristics of difference gate geometry of FinFET. Four of difference gate structure have been designed and simulated by GTS Framework TCAD software which is simulation the characteristics of FinFET device include drain currentvoltage, threshold voltage and subthreshold swing. Then, the electrical characteristics was compared. From the result found that the drain current depend on gate geometry of FinFET. The largest gate geometry of FinFET device was the rectangle shape with gate width at 66 nm, IDS about 19.8 mA and VTH = 0.5 V and the smallest gate geometry, the triangle shape with gate width at 52 nm and give IDS about 8.5 mA and Vth = 0.5 V.
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Defect distribution and yield analysis technique on silicon wafer
(2014-01-01)
Praepattarapisut, Warakorn
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Pengchan, Weera
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Phetchakul, Toempong
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Poyai, Amporn
This paper presents the defect distribution and yield analysis on silicon wafer. The generation and recombination lifetime were the key parameters and obtained from the current- voltage and the capacitance-voltage of diode characteristics for forward bias. Then 3D contour maps were plotted as defect distribution and can be analyzed for the whole wafer which is useful for the yield analysis of the defects that were caused from fabrication process. © (2014) Trans Tech Publications, Switzerland.
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Power loss analysis based on leakage currentin PN junctions
(2013-10-04)
Pengchan, Weera
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Phetchakul, Toempong
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Poyai, Amporn
This paper is proposed to analyze the power loss from leakage current in p-n junctions in case of non-uniform defects. The different geometry p-n junctions have been fabricated by a standard 0.8 micron CMOS technology. The diode fabricated by the ion implantation process with two different condition. The reverse current and voltage (I-V)characteristics at varied temperature of p-n junctions have been measured. The power loss coefficient can be extracted from the leakage current versus temperature. Form the derivative of leakage current with temperature, the power loss with prediction trend curve can be obtained. © (2013) Trans Tech Publications, Switzerland.

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