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Start date: 2020Subject: search.filters.subject.Capacitance multiplier

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    Design and Synthesis of Capacitance Multiplier Using LT1228s and a Grounded Capacitor
    (2026-01-01)
    Channumsin, Orapin
    ;
    Roongmuanpha, Natchanai
    ;
    Likhitkitwoerakul, Nutcha
    ;
    Tangsrirat, Worapong
    In this study, the design and synthesis of a grounded capacitance multiplier is discussed. The proposed circuit consists of two commercially available integrated circuits (ICs) named LT1228, together with a single grounded capacitor as a passive element. The transconductance gain of LT1228 allows for electronic control of the simulated equivalent capacitance value. The LT1228 transconductance gain is easily adjusted through the external bias current, which has a wide adjustable range of 1 µA to 1 mA. No component matching is required for the designed simulator. A non-ideal analysis of the proposed circuit has been investigated in detail. The workability of the proposed circuit and its application example as a first-order lowpass filter has been confirmed with the theoretical findings through PSPICE software. The results indicate that the proposed simulator has excellent performance and matches the theory.
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    Single Active Element Based Electronically Controllable Capacitance Multiplier
    (2022-07-15)
    Jaikla, Winai
    ;
    Huaihongthong, Pintira
    ;
    Siripongdee, Surapong
    ;
    Chaichana, Amornchai
    ;
    Suwanjan, Peerawut
    The realization of capacitance multiplier using the versatile active building block, namely voltage differencing differential difference amplifier (VDDDA) is presented in this paper. The realized capacitance multiplier is very simple consisting of one VDDDA, one MOS resistor (RM) and one grounded capacitor which is attractive for integration. The multiplication factor (KC) of the realized circuit can be electronically controlled via the bias current (IB) and control voltage (VC) without the need of any matching condition of active and passive element. Moreover, the multiplication factor can be adjusted to be more or less than one. The performances of the presented capacitance multiplier are verified through Pspice simulation using CMOS VDDDA in 0.18μm TSMC technology with ±0.9V power supplies. The multiplication factor is designed to be KC=2 by choosing VC=0.85V, IB=50μA and C=30 pF. The simulated multiplication factor is around 1.98. The simulated operational frequency range is around three decades (6.16 kHz-8.91MHz). The performances of the proposed circuit are also verified by the experiment using VDDDA implemented from the commercial ICs, AD830 and LM13700 with ±5V power supplies. The experiment is conducted under the same multiplication factor (KC=2) as the simulation by choosing RM=0.27 kω (1% passive resistor), IB=96.2μA and C=1nF. The experimental multiplication factor is around 2.06. The experimental operational frequency range is around three decades (1kHz-1.25MHz). By adjusting the bias current from 17.67μA to 400 μA, the experimental multiplication factor is controllable from 11.47 to 0.48. The percent deviation of the theoretical and experimental multiplication factor is lower than 5% when the value of bias current is greater than 39μA. These deviations stem from the effect of the parasitic capacitance and resistance in VDDDA. Moreover, the application example of the presented capacitance multiplier as the sinusoidal oscillator is presented. The performances of the presented oscillator verified via the experiment are well consistent with theoretical anticipation.
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    Floating capacitance multiplier realization based on commercially available integrated circuits
    (2022-06-01)
    Roongmuanpha, Natchanai
    ;
    Tangsrirat, Worapong
    This article is an attempt to present a tunable floating capacitance multiplier using commercially available integrated circuits, namely LT1228. The proposed design utilizes three LT1228s as active electronic components and only one capacitor as a passive component. The multiplication factor of the capacitance multiplier is electronically tunable via adjusting the external supply currents of the LT1228s. Besides, a careful analysis of the parasitic element effects is also included. To verify the practical features of the proposed floating capacitance multiplier circuit, several simulations using PSPICE program tool and extensive laboratory measurements were performed.
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    Practical Floating Capacitance Multiplier Implementation with Commercially Available IC LT1228s
    (2021-03-01)
    Roongmuanpha, Natchanai
    ;
    Tangsrirat, Worapong
    A practical realization of a tunable floating capacitance multiplier using commercially available integrated circuits, namely LT1228 is proposed. The synthetic capacitor utilizes only two IC LT1228s along with two passive components (one resistor and one capacitor). The capacitance multiplication factor is electronically controllable through the transconductance gain of the LT1228. The effects of non-ideal transfer gains and parasitic elements of the LT1228 on the circuit performance have been evaluated in detail. The applicability of the proposed floating capacitance multiplier as a second-order band-pass filter is also presented. The claimed theory is verified by several PSPICE simulations and experimental test results.
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    A Single Parameter Voltage Adjustable Immittance Topology for Integer- And Fractional-Order Design Using Modular Active CMOS Devices
    (2021-01-01)
    Sotner, Roman
    ;
    Jerabek, Jan
    ;
    Polak, Ladislav
    ;
    Prokop, Roman
    ;
    Jaikla, Winai
    A simple single parameter adjustable immittance concept designed with modular active devices, fabricated in I3T $25~0.35~\mu \text{m}$ 3.3 V CMOS process of ON Semiconductor, is introduced. The proposed devices employ an integer-order capacitor and specifically designed fractional-order capacitors (sometimes called constant phase elements). The proposed active topology consists of two simple active elements, namely a linearly voltage adjustable operational transconductance amplifier and a voltage differencing unity gain voltage follower/buffer, and only two passive elements, i.e. redundancy is minimized. The designed topology offers generation of an adjustable immittance having both the capacitive and inductive character. The importance of the order as well as the value of the pseudo-capacitance for design and analyzes are shown, including all important parasitic features for estimation of expected operational bandwidth which have to be considered in the design. The operational bandwidth is determined by high values of approximants of fractional-order capacities (225, 56 and $8.8~\mu \text{F}$ /seĉ1- $\alpha $ , where $\alpha $ represents the order equal to 0.25, 0.5 and 0.75, respectively). These parameters result into ranges between tens of Hz and units-tens of kHz. The adjustability of the transconductance from 70 to $700~\mu \text{S}$ by the driving voltage between 0.05 and 0.5 V offers approximately one decade change of equivalent capacitance and inductance. Laboratory-based experiments done with a fabricated prototype confirmed the theoretical presumptions.