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    Design of Constant Phase Elements for Adjustable Pseudocapacitance by a Single Driving Voltage Using Integrated Unipolar Transistor Fields
    (2026-01-01)
    Sotner, Roman
    ;
    Litovska, Anna
    ;
    Polak, Ladislav
    ;
    Jerabek, Jan
    ;
    Kledrowetz, Vilem
    This paper presents the design of a passive fractional-order element with tunable pseudocapacitance, enabling adaptable circuit behavior without additional power consumption. This is an important feature for modelling and characterization in natural systems, as well as in the field of electrical and electronic engineering, particularly for the design of instrumentation and sensing systems. The proposed topologies are based on integrated unipolar transistor arrays. Two implementations are demonstrated, with fractional orders of 0.22 and 0.5, offering pseudocapacitance adjustment ranges from 65 to 1 670 mikroF/s^0.78 and from 6.7 to 51 mikroF/s^0.5, respectively. Tuning is achieved through a DC bias voltage ranging from 0.8 to 10 V. The devices operate across nearly two decades of frequency, from approximately 100 Hz to 200 kHz, and support signal amplitudes in the hundreds of millivolts. Two application examples highlight their potential: electronic tuning of the center frequency in a fractional-order band-pass filter, and adjustment of the oscillation frequency in a fractional-order oscillator with a fixed 22.5 degrees phase shift between output waves. All concepts and results are experimentally validated in the laboratory.
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    MIOTA-Based Filters for Noise and Motion Artifact Reductions in Biosignal Acquisition
    (2022-01-01)
    Khateb, Fabian
    ;
    Prommee, Pipat
    ;
    Kulej, Tomasz
    This paper presents a new low-voltage CMOS structure for operational transconductance amplifier (OTA) exploiting the bulk-driven, the self-cascode and the multiple-input transistor techniques (MI). The multiple-input OTA (MIOTA) circuit operates in subthreshold region using 0.5V supply voltage and offers enhanced linearity. The MIOTA is developed for biopotential signal as well as electrocardiogram (ECG) signal processing circuit and it is exploited to design a 5th-order Chebyshev low-pass and 3rd-order band-pass filters with a dynamic range (DR) of 57.6 dB and 60.4 dB, and nanopower consumption of 50 nW and 60 nW, respectively. Due to the electronic tuning of cut-off frequency, the low-pass and band-pass filters are suitable for random noise and motion artifact noise reductions in biopotential signals. The circuits were designed in Cadence environment using the standard N-well 0.18~\mu TSMC CMOS technology. Intensive post-layout simulation results along with the process, voltage, temperature analysis (PVT) and Monte Carlo (MC) prove the robustness of the design. The chip area of the proposed MIOTA is 0.00725 mm<sup>2</sup>; ( 118~\mu \times 61.5\mu ). Compared with standard OTA the MIOTA offers simplification of filter topology and reduced number of active elements. In order to demonstrate these advantages, the MIOTA-based filter was also build using commercially available OTA LT1228. The experimental results of OTA LT1228 confirm both the filter functionality and the advantages of the proposed MIOTA.
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    Horizontal Magnetic Field MAGFET by Conventional MOSFET Structure
    (2018-07-02)
    Nakachai, Rattapong
    ;
    Poonsawat, Sawatdipong
    ;
    Sutthinet, Chalin
    ;
    Ruangphanit, Anucha
    ;
    Poyai, Amporn
    The MOSFET used as magnetic field sensor is presented. It is a conventional structure that has a source, a gate, a drain and a substrate or body terminal which fabricated by standard CMOS process. It detects the horizontal y-direction magnetic field in parallel and perpendicular to currents. The device is biased for channel current and substrate current. The mechanism is Hall Effect in current mode. The induced Lorentz's force deflects currents between drain current and substrate forward current causes output differential current. The relation shows linearly dependence between magnetic field density and output differential current. The relative sensitivity depends on amount of bias currents.
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    Simulation of MOSFET as horizontal magnetic MOSFET (MAGFET)
    (2017-12-14)
    Nakachai, Rattapong
    ;
    Phetchakul, Toempong
    ;
    Poonsawat, Sawatdipong
    ;
    Poyai, Amporn
    This work proposes the regular long channel MOSFET structure used as magnetic MOSFET (MOSFET that can detect magnetic field) in parallel direction (y-axis). The structure is regular MOSFET that has drain, gate, source and substrate (body). The mechanism of device is Hall effect in current mode between channel MOSFET current and substrate current in x-axis direction. The dimensions of channel MOSFET are 20 μm wide and 20 μm long. The channel and substrate currents are balance adjusted in the same values at 0.5, 1 and 1.5 mA. From the simulation results by TCAD sentaurus, the relative sensitivity of device is 0.01 T<sup>-1</sup> in y and - y direction, respectively. It can be used as magnetic sensor for one dimension in parallel field.
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    A Sub-100ppm/∘C Temperature-Compensated High-Frequency CMOS Relaxation Oscillator
    (2016-01-01)
    Sakphrom, Siraporn
    ;
    Georgiou, Pantelis
    ;
    Thanachayanont, Apinunt
    A temperature-compensated high-frequency CMOS integrated relaxation oscillator with low frequency variations is presented. A current-controlled oscillator topology is employed with a resistive source-degenerated transconductor and a current comparator to achieve high oscillation frequency and low power dissipation. The proposed oscillator was designed with process parameters from a standard 0.35-μm CMOS technology and a 2.5-V single power supply voltage. At a nominal oscillation frequency of 21 MHz, the total power dissipation of the circuit was 201 μW. Post-layout simulation results showed that the frequency variations were less than 34.16ppm/∘C over a temperature range of -40 to +120∘C.
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    A new model for predicting the effect of temperature and devices dimension on threshold voltage of PMOS in VLSI
    (2015-08-17)
    Ruangphanit, A.
    ;
    Poyai, A.
    ;
    Sakuna, N.
    ;
    Niemcharoen, S.
    ;
    Muanghlua, R.
    This paper presents a new model for predicting the effect of temperature and the devices dimension on the threshold voltage of PMOS. Temperature-dependent models have been developed including the temperature affect of surface potentials, intrinsic carrier concentration and energy band gap. The developed models have been used to study the temperature dependent and narrow channel width on the threshold voltage of PMOS. The new temperature coefficient for threshold voltage and the body-bias coefficient of threshold voltage of a big PMOS and a narrow channel width of MOSFET are proposed. The model can be implemented in simulation tools with the error is less than 3%.