Tooprakai, Sirapop

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A 1.2 v low-power true single-phase clock CMOS 2/3 prescalers
(2014-11-05)
Tooprakai, Siraphop
;
Tudsorn, Apirak
This paper presents a low-power true single-phase clock 2/3 prescalers at 1.2 V supply voltage. The true single-phase clock divider was developed to help achieve low power and highspeed. All simulation results have been carried out by using Hspice program simulator based on 0.13μm CMOS technology. The power consumption of the proposed circuit is less than that of the previous circuits. The prescaler is capable of operating from 0.5 to 9.7 GHz.
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Path loss comparison in 850 MHz and 1800 MHz frequency bands
(2016-09-06)
Bhupuak, Wiyada
;
Tooprakai, Siraphop
Nowadays people widely used mobile phone instead of using landlines phones. This paper proposes to compare the path loss in 850 MHz and 1800 MHz frequency bands by various path loss models. The path loss under terms of the transmitter height and the receiver height. The well known path loss model such as Walfisch-Ikegami (WI), SUI and Ericsson model used to simulate path loss by MATLAB. The results shown that when the longest distance WI model has the most path loss at the receiving antenna height is 1 and 5 meters. The path loss in the frequency bands 1800 MHz is greater than the path loss in the frequency bands 850 MHz under the same conditions. The path loss can be use to determine where to install the mobile base station with high quality. That means at the same distance if using the frequency band 1800 MHz for mobile network in the same technology will require to install the mobiles base station more than using frequency band 800 MHz.
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1V High speed E-TSPC 2/3 prescalers
(2019-07-01)
Lawang, Itthiphat
;
Tudsorn, Apirak
;
Tooprakai, Siraphop
This paper presents a 1V High Speed E-TSPC 2/3 Prescalers. The true single-phase clock divider was developed to constitute work faster and low power. All simulation results are performed using the Hspice simulator program. And uesd CMOS technology on 45 mm. The power consumption of the proposed circuit will consume less power than other circuits previously. The maximum input frequency for simulations of the suggested prescaler reaches up to 24GHz at 1V supply voltage.
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Design high speed and low power hybrid full adder circuit
(2018-12-24)
Lueangsongchai, Sathaporn
;
Tooprakai, Siraphop
This paper presents 1-bit hybrid full adder cells circuit scheme that high speed and low power consumption. This Full adder cells circuit is designed utilization of XOR gate, XNOR gate, pass logic gate and transmission gate. Result of simulation by HSPICE program based on 16 nm CMOS technology with 0.9V power supply voltage and maximum frequency at 8GHz.
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A 1.1-V Low power true single-phase clock 2/3 prescaler
(2017-10-19)
Tooprakai, Siraphop
;
Wisetphanichkij, Sompong
;
Tudsorn, Apirak
This paper is proposed a low-power CMOS 2/3 prescaler using true single-phase technique on 45 nm CMOS technology with 1.1 V. The true-single-phase clock divider is used to achieve low power. The prescaler is capable of operating from 1 to 16 GHz. When operating at 1 GHz, it saves more power consumption compared to that of a conventional circuit and lowpower true single-phase clock CMOS 2/3 prescalers circuit operating in divide-by-2 mode and in divide-by-3 mode, respectively.
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Low power CMOS full adder cells
(2012-10-02)
Sudsakorn, Attapon
;
Tooprakai, Siraphop
;
Dejhan, Kobchai
This paper presents low power CMOS full adder cells. The full adder cells are utilization to low power by using XOR and XNOR gate architectures with pass transistor logic and transmission gate. All simulation results have been carried out by using HSPICE program simulator based on 22 nm CMOS technology at 1.2 V supply voltages. The operating frequency is 250 MHz. In comparison with other 1 bit adder cells, simulation results show that have used low power consumption and power delay product of SUM and C <inf>OUT</inf>. © 2012 IEEE.
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Estimation on protection distance between analog TV and digital TV in adjacent channel at terrestrial television
(2017-10-19)
Chomsuk, Kinupong
;
Tooprakai, Siraphop
Office of the National Broadcasting and Telecommunication Commission (NBTC), the Thai governmental organization decided to launch digital broadcasting. The implementation has to carry by the broadcasting license; the digital transmission testing has to carry on broadcasting on channel 30 while the analog television has to broadcast on channel 29. The adjacent channel interference must occur between analog television signal and digital television signal because of 20 MHz spacing between both signals. This paper proposes the experimental study of testing in order to measure and determine the degradation caused by the analog PAL television signal interferences on the digital television signal.

Tooprakai, Sirapop

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