Wongprasert, Yothin
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Wongprasert, Yothin
Alternative Name
Wongprasert, Y.
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yothin.wo@kmitl.ac.th
7 results
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Item type:Publication, The effects of geometrical capacitance components of LOCOS diode in VLSI(2019-03-01); The effects of geometrical capacitance components of LOCal Oxidation of Silicon (LOCOS) diode in Very Large Scale Integrated circuit (VLSI) are proposed. For the correct circuit model simulation, the model of the device must be accurate and consistence with the SPICE models. The rectangular structure (L=400 μm, W=200 μm), the multi-fringe structure 1 (L=400 μm, W=4 μm, no. strips =50) and the multi-fringe structure 2 (L= S μm, W= Sμm, no. sample =1200) have been designed. These extraction methodologies show the area capacitance component, the peripheral capacitance component and the corner capacitance component at the field oxide side. The BSIM 3v3 junction capacitance models are proposed also. The comparison is made to check the accuracy of the parameter models. The results showed a low level error. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, The diamond crystal nucieation by combustion activation CVD(2008-12-01); ; Sato, K.This paper presents the diamond nucleation using combustion activation chemical vapor deposition (CACVD) by 0.95 volumetric ratio of O <sup>2</sup>/C<sup>2</sup>H<sup>2</sup> under atmospheric pressure. The main point of our work is to develop the CACVD technique for synthesize the semiconductor materials, which is developed for electronic devices application. The surface nucleation of substrate was studied by using surface pretreatment. The results of surface nucieation on mirror-silicon, polished silicon by diamond powder, silicon-dioxide (Sio<inf>2</inf>), and polished Sio<inf>2</inf> by diamond powder, are significantly different. It can be concluded that the silicon-dioxide mask technique is useful for nucleated diamond protection whereas the polished silicon by diamond powder is suitable for nucleated diamond generation. These techniques are applied for the pattern fabrication. © 2008 Trans Tech Publications, Switzerland. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Rapid synthesis of potassium sodium niobate (K 1/2Na 1/ 2NbO3) lead-free piezoelectric powder using the combustion method(2013-12-01); ; ; Potassium sodium niobate (K1/<inf>2</inf>Na1/<inf>2</inf>NbO<inf>3</inf>) powder was synthesized successfully by the combustion synthesis. The raw materials of KNO<inf>3</inf>, NaNO<inf>3</inf> and Nb<inf>2</inf>O<inf>5</inf> were used with glycine as fuel. The thermal behaviour of the precursor was determined using thermo gravimetric analysis (TGA) and derivative thermo gravimetric (DTG) analysis. The conditions for preparing perovskite phase formation, influence of the fuel-to-oxidizer molar ratio, and crystal structure were characterized by the X-ray diffraction technique (XRD) and Fourier transform infrared (FTIR) spectroscopy. The morphology and particle size were investigated through a scanning electron microscope (SEM). © 2013 Copyright Taylor and Francis Group, LLC. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Gamma-radiation Induced Degradation of the Electrical Characteristics of NMOSFETs(2022-01-01); In this paper, we present the gamma-radiation induced degradation of the electrical characteristics of N-channel Metal Oxide Semiconductor Field Effect Transistors (NMOSFETs). The exposure was done with a<sup>60</sup>Co gamma-ray source over the total dose range of 1 kGy to 10 kGy, with a dose rate of 3.9 kGyhr. The effects of irradiation induced degradation on device parameters such as threshold voltage, low field mobility, device transconductance (G<inf>m</inf>), saturation drain current, off state leakage current and subthreshold swing were investigated. The threshold voltage was determined using the linear extrapolation method. The device dimensions with Wide/ Long channel that excluded the Narrow Channel Effect (NCE) and the Short Channel Effect (SCE) were measured. The results showed that the threshold voltage, device transconductance and low field mobility decreased but the saturation drain current, off state leakage current and subthreshold swing increased as the gamma irradiation increased. Finally, the macro parameter models were investigated and discussed. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Effect and Determination of Oxide Trapped Charge and Interface Trapped Charge Density of Threshold Voltage Shift in Irradiated MOSFET by Subthreshold Methodology(2023-10-01); This paper presents the effects and determination of oxide and interface trapped charge density of threshold voltage shift in irradiated MOSFET by subthreshold methodology. The designed dimension, channel width per channel length (W/L) is 20 µm/20 µm. The threshold voltage is extracted by a linear extrapolation methodology. The over all threshold voltage shifts are caused by oxide trapped charge and interface trapped charge. The subthreshold methodology determines the interface trapped charge. The<sup>60</sup>Co gamma-ray source was used for irradiation to a total dose of 10 kGy. The results showed that the threshold voltage shift is approximately-24 mV/kGy for NMOS and-27 mV/kGy for PMOS. The subthreshold swing shift is approximately 1.2 mV/dec.kGy for NMOS and 0.9 mV/dec.kGy for PMOS. The oxide trapped charge density N<inf>OT</inf> and interface trapped charge density N<inf>IT</inf> are found to be increased in NMOS and PMOS respectively. The ratio of ΔN<inf>OT</inf>/ΔN<inf>IT</inf> was approximately 2.2 times for NMOS and 2.8 times. Due to the structure, the channel of NMOS is a surface channel whereas the channel of PMOS is a buried channel. Finally, the effect of gamma irradiation on the PMOS was greater than the effect on NMOS observed from the change in threshold voltage and the ratio of ΔN<inf>OT</inf>/ΔN<inf>IT.</inf>. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Combustion synthesis of lead-free piezoelectric alkali metal niobate family(2013-01-01); ; ; Nano-crystalline alkali metal niobate (ANbO<inf>3</inf>; A = K and Na) powders were synthesized by the combustion of nitrate compounds and Nb <inf>2</inf>O<inf>5</inf> using glycine as the fuel. The chemical reaction, nucleation mechanisms and influence of the fuel-to-oxidizer ratio to phase formation were studied. The precursor and product powders were characterized, using the thermo gravimetric analysis (TGA), Fourier transform infrared (FT-IR) spectroscopy, X-ray diffraction (XRD) technique, and scanning electron microscopy (SEM). Different fuel-to-oxidizer ratios were found to be a key factor of the process. As-prepared and calcined powders provided the perovskite structure with a nano-scale of mean crystalline size. © 2013 Copyright Taylor and Francis Group, LLC. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, The effects of temperature and device demension of MOSFETs on the DC characteristics of CMOS inverter(2012-10-02); ; Niemcharoen, S.The CMOS fabrication technology requires both n-channel (NMOS) and p-channel (PMOS) transistors be built on the same substrate. To ensure the reliability of the circuit performance over the temperature range, the circuits must be designed accommodate the basic variations parameters as a function of parameter. The temperature dependence of the MOSFET parameters as well as the small dimension effects on the dc characteristics of submicrometer CMOS inverters operated over the temperature range of 27- 125 degree Celsius are presented. The results show that the threshold voltage temperature coefficient (TCV) of both devices increased as the channel width decreased. PMOS has a larger affect more than NMOS because of a buried channel device. The Voltage Transfer Characteristics (VTC) of an inverter shows a symmetrical gate at WR is 2.0. However, the narrow channel effect, threshold voltage matching and ratio B <inf>R</inf> are key problem of CMOS inverter worked. Finally, these results will support the process engineer, circuit designer to improve device performance in the next fabrication. © 2012 IEEE.