Wongprasert, Yothin
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Wongprasert, Yothin
Alternative Name
Wongprasert, Y.
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Email
yothin.wo@kmitl.ac.th
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Item type:Publication, The effects of geometrical capacitance components of LOCOS diode in VLSI(2019-03-01); The effects of geometrical capacitance components of LOCal Oxidation of Silicon (LOCOS) diode in Very Large Scale Integrated circuit (VLSI) are proposed. For the correct circuit model simulation, the model of the device must be accurate and consistence with the SPICE models. The rectangular structure (L=400 μm, W=200 μm), the multi-fringe structure 1 (L=400 μm, W=4 μm, no. strips =50) and the multi-fringe structure 2 (L= S μm, W= Sμm, no. sample =1200) have been designed. These extraction methodologies show the area capacitance component, the peripheral capacitance component and the corner capacitance component at the field oxide side. The BSIM 3v3 junction capacitance models are proposed also. The comparison is made to check the accuracy of the parameter models. The results showed a low level error. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, The diamond crystal nucieation by combustion activation CVD(2008-12-01); ; Sato, K.This paper presents the diamond nucleation using combustion activation chemical vapor deposition (CACVD) by 0.95 volumetric ratio of O <sup>2</sup>/C<sup>2</sup>H<sup>2</sup> under atmospheric pressure. The main point of our work is to develop the CACVD technique for synthesize the semiconductor materials, which is developed for electronic devices application. The surface nucleation of substrate was studied by using surface pretreatment. The results of surface nucieation on mirror-silicon, polished silicon by diamond powder, silicon-dioxide (Sio<inf>2</inf>), and polished Sio<inf>2</inf> by diamond powder, are significantly different. It can be concluded that the silicon-dioxide mask technique is useful for nucleated diamond protection whereas the polished silicon by diamond powder is suitable for nucleated diamond generation. These techniques are applied for the pattern fabrication. © 2008 Trans Tech Publications, Switzerland. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, 18650 Battery Real Time Output Resistance Test(2020-04-01); - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Characteristics of synthesized diamond films by using CACVD techniques at high temperatures(2010-01-01); Pongsai, S. B.This paper presents synthesized diamond films by using combustion activated chemical vapor deposition (CACVD) techniques. The characteristics of diamond films have been studied at wide ranges of temperature (30-400°C). The resistance of diamond films has been determined for hydrogen termination times of 5, 10, 15, and 20 minutes, and at the operation temperatures of 500, 600, and 700°C. The investigation found that, at 30°C a synthesized diamond film has a high resistance (10<sup>10</sup> Ω), whereas at high temperatures (100-400°C) the resistance has decreased from 4.04 MΩ to 2.42 MΩ. The result obtained from the hydrogen termination showed that the resistance has decreased by 10<sup>5</sup>-10<sup>6</sup> Ω (at 30° C). Summarily, it can be stated that the higher the hydrogen termination times and operation temperatures, the lower the resistance of diamond films. © (2010) Trans Tech Publications. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, The effects of temperature and device demension of MOSFETs on the DC characteristics of CMOS inverter(2012-10-02); ; Niemcharoen, S.The CMOS fabrication technology requires both n-channel (NMOS) and p-channel (PMOS) transistors be built on the same substrate. To ensure the reliability of the circuit performance over the temperature range, the circuits must be designed accommodate the basic variations parameters as a function of parameter. The temperature dependence of the MOSFET parameters as well as the small dimension effects on the dc characteristics of submicrometer CMOS inverters operated over the temperature range of 27- 125 degree Celsius are presented. The results show that the threshold voltage temperature coefficient (TCV) of both devices increased as the channel width decreased. PMOS has a larger affect more than NMOS because of a buried channel device. The Voltage Transfer Characteristics (VTC) of an inverter shows a symmetrical gate at WR is 2.0. However, the narrow channel effect, threshold voltage matching and ratio B <inf>R</inf> are key problem of CMOS inverter worked. Finally, these results will support the process engineer, circuit designer to improve device performance in the next fabrication. © 2012 IEEE.