Pengchan, Weera
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Preferred name
Pengchan, Weera
Alternative Name
Pengchan, W.
Main Affiliation
Email
weera.pe@kmitl.ac.th
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Item type:Publication, The defects analysis in CMOS fabrication by arrhenius activation energy technique(2011-10-04); ; Poyai, AmpornLow power consumption device can be realized by low junction leakage current. This leakage current relates to the defects in the depletion region of p-n junction. Among variety process steps, implantation step may generate defects. Therefore, the implantation-induced defects have been studied from the activation energy which has been obtained from the leakage current of p-n junction. The different geometry p-n junctions have been fabricated by a standard CMOS technology. The current-voltage (I-V) and high frequency capacitance-voltage (C-V) characteristics of p-n junctions with temperature dependence have been measured. The electrically active defects from implantation process can be extracted from the junction generation current density versus temperature. Base on this analysis, it will be demonstrated that the implantation-induced defects have been found in p<sup>+</sup>-n-well more than in n<sup>+</sup>-p-substrate. Finally, the possible nature of the defect will be discussed. © 2011 IEEE. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Yield analysis by poisson yield model based on the defect analysis with derivative method(2014-01-01); ; Poyai, A.This paper presented the corresponding between the classical Poisson's yield equation prediction and wafer actual yield on the silicon wafer with 0.8 μm CMOS technology. The defect analysis with derivative method, current - voltage and capacitance-voltage of diode characteristic measurement, is used to define the defect in p-n junction on silicon wafer. The different sampling numbers of chips are used to calculate the yield. Finally the calculated data and actual would be compared and found that at sampling number is 25, the tolerance from actual yield is less than 2%. © 2014 IEEE.