Pengchan, Weera
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Pengchan, Weera
Alternative Name
Pengchan, W.
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weera.pe@kmitl.ac.th
20 results
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Item type:Publication, The defects analysis in CMOS fabrication by arrhenius activation energy technique(2011-10-04); ; Poyai, AmpornLow power consumption device can be realized by low junction leakage current. This leakage current relates to the defects in the depletion region of p-n junction. Among variety process steps, implantation step may generate defects. Therefore, the implantation-induced defects have been studied from the activation energy which has been obtained from the leakage current of p-n junction. The different geometry p-n junctions have been fabricated by a standard CMOS technology. The current-voltage (I-V) and high frequency capacitance-voltage (C-V) characteristics of p-n junctions with temperature dependence have been measured. The electrically active defects from implantation process can be extracted from the junction generation current density versus temperature. Base on this analysis, it will be demonstrated that the implantation-induced defects have been found in p<sup>+</sup>-n-well more than in n<sup>+</sup>-p-substrate. Finally, the possible nature of the defect will be discussed. © 2011 IEEE. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Study on temperature effect on p-n and Zener junction for PTAT temperature sensor(2008-10-06); ; ; Supadech, J.Research on a new compact BJT PTAT temperature sensor structure has been reported. The zener junction-connected BJT transistor and Base-Emitter voltage of transistor can be temperature dependent. The performance of new compact PTAT circuit can be improved by using difference in thermal characteristics between p-n and zener junction. ΔV/ΔT can be further increased by connecting p-n and zener junction in series. The results show that ΔK/ΔT of the circuit increased by 6.77 timed or 85% compared with conventional PTAT and connecting two p-n and zener junction in series. The result show that ΔK/ΔT of the circuit increased by 3.3 timed or 70%compared with proposed circuit the output voltage is large enough so that it can be used directly without additional amplifier. This also improves S/N ratio and the unique linearity of PTAT is still preserved. The working temperature of circuit is between -60°C to 160°C © 2008 IEEE. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Magnetotransistor sensing by the difference of base and collector current(2004-12-01); - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Power loss analysis based on leakage currentin PN junctions(2013-10-04); ; Poyai, AmpornThis paper is proposed to analyze the power loss from leakage current in p-n junctions in case of non-uniform defects. The different geometry p-n junctions have been fabricated by a standard 0.8 micron CMOS technology. The diode fabricated by the ion implantation process with two different condition. The reverse current and voltage (I-V)characteristics at varied temperature of p-n junctions have been measured. The power loss coefficient can be extracted from the leakage current versus temperature. Form the derivative of leakage current with temperature, the power loss with prediction trend curve can be obtained. © (2013) Trans Tech Publications, Switzerland. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Effect of base width and implantation dose on performance of 3-terminal magnetotransistor(2007-12-01); ; Klunngien, NipapanThis paper presents the effect of base width and implantation dose on electrical carriers in the magnetotransistor deflected by the Lorentz force (F<inf>L</inf>) from magnetic field. The structure of magnetotransistor is designed like a structure of a PNP bipolar junction transistor which comprises of 3 terminals, i.e., emitter, collector and base. The base width (L) is varied (10, 20 and 30 μm) where the spacing between collector and base is fixed at 40 μm. The emitter and collector regions are doped with boron (BF <inf>2</inf>) at the dose of 3×10<sup>15</sup>, 5×10<sup>15</sup> and 1×10<sup>16</sup> ions/cm<sup>2</sup>. It is found that the sensitivity is increased when increasing L and the implantation dose. It is also demonstrated that the linear relationship between the output voltage of the magnetotransistor circuit and magnetic field can be obtained. © 2007 IEEE. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Effect of temperature on 16 nm n-FiNFET(2018-01-01)This research presents the effect of temperature that influence to the performance of 16 nm SOI n-FinFET structure. The structure has created with structure tool on GTS Framework. The transistor has 1 nanometer HfO<inf>2</inf> gate oxide with all metal contact and biased on Minimos-NT tool, with variation of temperatures from 300 K to 420 K with 30 K per step. The result found the decrease in saturation current, threshold voltage and mobility. The temperature brought electron and rose the density of electron as the potential from power supply that energized to the structure. They made mobility fall with them rising. The temperature makes a performance of FinFET structure. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Extraction of defect in doping silicon wafer by analyzing the lifetime profile method(2008-01-01); ; Poyai, A.The total leakage current in silicon p-n junction diodes compatible with 0.8 μm CMOS technology is investigated. The generation lifetime is a key parameter for the leakage current, which can be obtained from the current-voltage (I-V) and the capacitance-voltage (C-V) characteristics. As will be shown, the electrically active defect from ion implantation process generated in p-n junction can be extracted from the generation current density. © 2008 Trans Tech Publications, Switzerland. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Optical Absorption and Bandgap Modulation in Diamond-Like Carbon Films for Anti-Reflection(2026-01-01); Diamond-like carbon (DLC) films were deposited onto glass and silicon substrates utilizing Electron Cyclotron Resonance Chemical Vapor Deposition (ECR-CVD) with an Argon/Acetylene gas mixture. Substrate biases were varied (0V,-55V,-100V) for both nitrogen-doped and undoped films. Optical band gap (Eg) decreased with increasing negative substrate bias specifically from 2.6 eV to 2.2 eV for nitrogen-doped DLC and from 1.6 eV to 1.3 eV for undoped DLC. Nitrogen doping generally results in films with wider band gaps compared to undoped films at equivalent biases to sp hybrid bond formation increasing bias reduces the band gap within each film type. I-V measurements revealed an increase in open-circuit voltage from approximately 0.648 V to a range of 0.678–0.698 V for cells incorporating nitrogen-doped DLC. This improvement is attributed to enhanced corrosion resistance and electrical conductivity suggesting the suitability of nitrogen-doped DLC for photovoltaic applications. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, The local generation and recombination lifetime based on forward diode characteristics diagnostics(2013-01-01); ; Poyai, AmpornThis paper is proposed to extract the local carrier generation and recombination lifetime from forward characteristics of diode. The different geometry p-n junctions have been fabricated by a standard CMOS technology. Among a variety process steps, implantation step may generate defects. Therefore, the local implantation-induced defects have been studied from the defect activation energy, which has been obtained from the ratio of the local carrier generation and recombination lifetime. The forward current-voltage (I-V) and high frequency capacitance-voltage (C-V) characteristics of p-n junctions have been measured in order to obtain the local carrier generation and recombination lifetime. The calculated activation energy from this method gave reasonable values comparing with the ones obtained from the Arrhenius plot of the reverse current. © 2011 Elsevier B.V. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Yield analysis by poisson yield model based on the defect analysis with derivative method(2014-01-01); ; Poyai, A.This paper presented the corresponding between the classical Poisson's yield equation prediction and wafer actual yield on the silicon wafer with 0.8 μm CMOS technology. The defect analysis with derivative method, current - voltage and capacitance-voltage of diode characteristic measurement, is used to define the defect in p-n junction on silicon wafer. The different sampling numbers of chips are used to calculate the yield. Finally the calculated data and actual would be compared and found that at sampling number is 25, the tolerance from actual yield is less than 2%. © 2014 IEEE.