Pengchan, Weera

Preferred name

Pengchan, Weera

Alternative Name

Pengchan, W.

Main Affiliation

School of Engineering

weera.pe@kmitl.ac.th

Now showing 1 - 10 of 20

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The new design for magnetoresistance effect on hall plate structure
(2012-10-02)
Phetchakul, T.
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Taisettavatkul, P.
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Pengchan, W.
;
Yamwong, W.
;
Poyai, A.
This paper presents the new design which contributes to magnetoresistance effect on Hall plate by compared with series resistance structure by Sentaurus TCAD program. A new design creates zero Hall voltage area which the carriers move and deflect freely. The Hall plate structure is n-type silicon with 400 μm length, 100 μm width and 1 μm thickness. Both designs have percentage of magnetoresistance effect about 20% at doping concentration 2×10 15cm -3, temperature 300K at magnetic field 3 Tesla. A new design on Hall plate structure is easier than the classical series resistance and has no effect of metal space which is in series resistance structure. © 2012 IEEE.
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Optical and electrical properties of diamond-like carbon thin film with deposition by ecr-cvd system
(2019-01-01)
Srisantirut, Tanawit
;
Pengchan, Weera
In this paper, evolution of optical and electrical properties of diamond-like carbon (DLC) films deposited by ECR-CVD system are reported. By varying the deposition different substrates bias (0,-55,-100 V) and volume amount of C2H2 from 40 to 55 cc onto substrate Si/TiN and quarts. The structure of the DLC films were analyzed from Raman spectroscopy. DLC films deposited bias at-100 V and C2H2 at 40 cc show excellent optical transmittance and high resistivity. As a result, ID/IG ratio corresponds to the optical transmittance and resistivity with ID/IG ratio decreased making the film like to the diamond. Most importantly, the transparency and resistivity properties of the DLC films can be tailored to approaching diamond by adjusting substrates bias and volume C2H2, is important to many applications, which is improve film properties.
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Improved extraction of the local carrier generation lifetime from forward diode characteristics
(2012-01-01)
Pengchan, Weera
;
Phetchakul, Toempong
;
Poyai, Amporn
This paper is proposed to extract the local carrier generation lifetime from forward current-voltage (I-V) characteristics of p-n junctions in case of non-uniform defects. The different geometry p-n junctions have been fabricated by a standard CMOS technology. The forward I-V and high frequency capacitance-voltage (C-V) characteristics of p-n junctions have been measured. The recombination current density can be extracted from the area forward current density by subtracting with the area diffusion current density. Form the recombination current density, the local generation and recombination lifetime can be obtained.
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Three-Phase Oscillator with Cascade Ability Using Voltage Current Conveyor
(2024-01-01)
Buakaew, Seangrawee
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Narksarp, Wipavan
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Choeysombat, Kamonthip
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Kanjanawiwin, Juthamas
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Atiwongsangthong, Narin
This paper presents a new circuit configuration employing voltage current conveyors (VCII) in conjunction with a minimal number of passive elements to achieve a voltage mode sinusoidal oscillator with a 3 -phase differential output. The proposed circuit features a straightforward architecture, with all passive elements connected to low-impedance nodes. Consisting solely of identical VCIIs without multiple outputs, the circuit facilitates the cascading of the 3 -phase outputs without requiring supplementary buffering. Simulation results obtained through PSPICE, along with experimental validation using commercial ICs, are provided to substantiate the efficacy of the proposed circuit.
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Defect distribution and yield analysis technique on silicon wafer
(2014-01-01)
Praepattarapisut, Warakorn
;
Pengchan, Weera
;
Phetchakul, Toempong
;
Poyai, Amporn
This paper presents the defect distribution and yield analysis on silicon wafer. The generation and recombination lifetime were the key parameters and obtained from the current- voltage and the capacitance-voltage of diode characteristics for forward bias. Then 3D contour maps were plotted as defect distribution and can be analyzed for the whole wafer which is useful for the yield analysis of the defects that were caused from fabrication process. © (2014) Trans Tech Publications, Switzerland.
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The influence of gate scaling to electrical characteristics on n-MOS FinFET
(2017-05-31)
Patchrasardtra, Nuttapong
;
Pengchan, Weera
This paper investigates effects from gate scaling in Tri-gate FinFET structure by simulation method, to avoid problems and improve a structure to be good prototype. The experiments used GTS framework for simulation. Start from 20 nm device, then scaling to 22 nm 28 nm and 32 nm. Therefrom Minimos-NT function has used for biasing to giving two electrical characteristics as the drain current saturation and the threshold voltage. From these consequences can offer the subthreshold swing and the drain-induced barrier lowering by calculation. The results found that threshold voltage inversely proportional to saturated drain current, the subthreshold swing and the drain-induced barrier lowering. The short channel effect has affected to 20 nm model by highest DIBL. Therefore should be adjust the gate length and the oxide thickness properly to improve this effect.
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Influence of Temperature to Electron Mobility on Top of Channel in 14 nm n-FinFET
(2017-01-01)
Patcharasardtra, Nuttapong
;
Pengchan, Weera
he temperature behavior that influential to the electron mobility on top surface in 14 nanometer FinFET channel. The Mobility could find on I-V characterizing simulation process and giving the result from the TCAD software by biasing on the FinFET structure with gate voltage at 1 volt and the drain-source voltage from 0 Volt to 1 Volt to obtain the saturation drain current from I-V characteristic. The Electron mobility was lowering by increasing the temperature from 303K (30°C) to 353K (80°C). This FinFET structure gave the I<inf>DS (Sat)</inf> about 29 µA and gave mobility at V<inf>DS</inf> = 0 Volt about 575 cm2/Vs, at V<inf>DS</inf> = 1 Volt, the mobility dramatically down to 3.4 cm2/Vs.
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The defects analysis in CMOS fabrication by arrhenius activation energy technique
(2011-10-04)
Pengchan, Weera
;
Phetchakul, Toempong
;
Poyai, Amporn
Low power consumption device can be realized by low junction leakage current. This leakage current relates to the defects in the depletion region of p-n junction. Among variety process steps, implantation step may generate defects. Therefore, the implantation-induced defects have been studied from the activation energy which has been obtained from the leakage current of p-n junction. The different geometry p-n junctions have been fabricated by a standard CMOS technology. The current-voltage (I-V) and high frequency capacitance-voltage (C-V) characteristics of p-n junctions with temperature dependence have been measured. The electrically active defects from implantation process can be extracted from the junction generation current density versus temperature. Base on this analysis, it will be demonstrated that the implantation-induced defects have been found in p+-n-well more than in n+-p-substrate. Finally, the possible nature of the defect will be discussed. © 2011 IEEE.
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Study on temperature effect on p-n and Zener junction for PTAT temperature sensor
(2008-10-06)
Songmalai, P.
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Phetchakul, T.
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Pengchan, W.
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Ratanaudomphisut, E.
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Supadech, J.
Research on a new compact BJT PTAT temperature sensor structure has been reported. The zener junction-connected BJT transistor and Base-Emitter voltage of transistor can be temperature dependent. The performance of new compact PTAT circuit can be improved by using difference in thermal characteristics between p-n and zener junction. ΔV/ΔT can be further increased by connecting p-n and zener junction in series. The results show that ΔK/ΔT of the circuit increased by 6.77 timed or 85% compared with conventional PTAT and connecting two p-n and zener junction in series. The result show that ΔK/ΔT of the circuit increased by 3.3 timed or 70%compared with proposed circuit the output voltage is large enough so that it can be used directly without additional amplifier. This also improves S/N ratio and the unique linearity of PTAT is still preserved. The working temperature of circuit is between -60°C to 160°C © 2008 IEEE.
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Electrical characteristics of different gate geometry of FinFET
(2016-01-01)
Patcharasardtra, Nuttapong
;
Pengchan, Weera
This paper proposed to the electrical characteristics of difference gate geometry of FinFET. Four of difference gate structure have been designed and simulated by GTS Framework TCAD software which is simulation the characteristics of FinFET device include drain currentvoltage, threshold voltage and subthreshold swing. Then, the electrical characteristics was compared. From the result found that the drain current depend on gate geometry of FinFET. The largest gate geometry of FinFET device was the rectangle shape with gate width at 66 nm, IDS about 19.8 mA and VTH = 0.5 V and the smallest gate geometry, the triangle shape with gate width at 52 nm and give IDS about 8.5 mA and Vth = 0.5 V.
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Pengchan, Weera

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