Moungnoul, Phichet

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Moungnoul, Phichet
Alternative Name
Moungnoul, P.
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Email
phichet.mo@kmitl.ac.th

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    A memristor emulator circuit based on operational transconductance amplifiers
    (2015-08-17)
    Kumngern, Montree
    ;
    Moungnoul, Phichet
    This paper introduces a memristor emulator circuit based on operational transconductance amplifiers. This emulator circuit is imitated the behavior of a titanium dioxide memristor model using commercial available integrated circuit. Thus, the hardware of proposed emulator circuit can be built using devices that find in the market. Also the circuit can be tested in both simulations and experiments which can be used as a teaching aid and for real circuit applications. Simulation and experimental results are given as agree well with theory.
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    Comparison of frequency reuseschemes for LTE micro-macro cells
    (2018-07-02)
    Chaiwongkhan, Udornphan
    ;
    Sato, Tomoaki
    ;
    Matathong, Samakom
    ;
    Moungnoul, Phichet
    LTE networks offer high capacity and high performance. Frequency Reuse schemes used in LTE network planning are optimized using inter-cell interference. Macro cells were install for large coverage area, but channel capacity is limited. Micro/macro technique used for increase capacity in the need high traffic area. The limiting factor the influences LTE performance is the interference from neighboring cells. This paper proposes FFR (Fraction Frequency Reuse) for micro/macro cells with sectoring. Micro/macro cells coordinated model is investigated. Simulation results to compare the capacity of micro/macro cell model cause of different number of carriers.
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    Throughtput investigated of coexistence Wi-Fi and LTE-U
    (2019-11-01)
    Moungnoul, Phichet
    ;
    A-Mapat, Narongchon
    Implementation of the mobile network provider to improve the network performance and the resources optimization by implemented coexistence LTE-TDD, LTE-FDD network and Wi-Fi technology. The main interference is the adjacent cell interference (ACI) from coexisting network/technology, which affected to the network performance. This paper is investigated LTE/Wi-Fi technique in coexistence LTE-FDD/TDD. Results show the distance between 50-60 m and Wi-Fi access point should not over 12 given the best system. The throughput compared with normal case will describe in this paper.
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    Hardware amount evaluation of the improved WEP on an FPGA
    (2013-09-02)
    Sato, Tomoaki
    ;
    Moungnoul, Phichet
    The spread of smart phones means the traffic capacity stringent of mobile communications. One way of solving the problem of traffic capacity is the use of a Wi-Fi hotspot. The majority of Wi-Fi hotspots are used WEP (Wired Equivalent Privacy) as a cipher. Nevertheless, the method of deciphering WEP has already been clarified. Some deciphering programs can execute deciphering of WEP in several seconds. To solve this problem, an improved WEP has been proposed. The features of the improved WEP are a compatible algorithm with WEP and strengthening of cipher strength. The improved WEP algorithm has been evaluated only on software and has not been implemented on hardware. On the other hand, ciphers for a Wi-Fi LAN are implemented on an FPGA (Field-Programmable Gate Array) as well as a system LSI and is used in various devices. Additionally, it is important that the size of the processing unit is small. In this paper, the improved WEP is implemented on an FPGA. Then, the number of elements and registers of the improved WEP is compared with that of a conventional WEP. As a result, it is shown that hardware amount of the improved WEP hardly increases. Besides, it is proposed that a method to increase the cipher strength of the improved WEP by utilizing the characteristics of an FPGA and wave-pipelining. © 2013 IEEE.
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    A connection block implemented in the RTL design for delay time equalization of wave-pipelining
    (2015-01-01)
    Sato, Tomoaki
    ;
    Chivapreecha, Sorawat
    ;
    Moungnoul, Phichet
    Field-programmable gate arrays (FPGAS) which have many advantages are used in various devices. Use of the FPGAS is not only prototyping and verification of circuits but also an important part of the commercial products. A CPU of hardcore is required in the FPGAS. But it has a problem with the architecture of the CPU is limited. The method of solving these problems is developing a system on a chip (SoC) which is equipped with FPGAS and a customized CPU. From the view point of ease of design and shortening a design period, development techniques on a register-transfer level (RTL) using a standard cell library are essential. On the other hand, applying this method without using a design technique has a problem in terms of throughput. In this paper, a connection block for routing using wave-pipeline technique is proposed to solve the throughput problems. This block is evaluated, and it is shown that it is useful for wave pipeline operation.
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    Packet filtering circuits for smart phones
    (2012-12-01)
    Sato, Tomoaki
    ;
    Moungnoul, Phichet
    ;
    Fukase, Masa Aki
    Security measures for smart phones are important. Anti-virus software for smart phones can be used and the process consumes CPU resources. The CPUs of them are powerless CPU for an embedded system and those operations consume battery power. In this paper, the authors propose packet filtering circuits for smart phones. The packet filtering circuits are a firewall. Using the firewall is a means to protect smart phones from computer viruses and unauthorized access. In addition, they are used to control the power consumption and to reduce of detecting units for unauthorized access. The features of the circuits are to achieve those functions without reconstructing circuits. The operations of the circuits are verified by gate-level simulations.
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    RCA on FPGAs designed by the RTL design methodology and wave-pipelined operation
    (2016-09-06)
    Sato, Tomoaki
    ;
    Chivapreecha, Sorawat
    ;
    Moungnoul, Phichet
    ;
    Higuchi, Kohji
    Field-programmable gate arrays (FPGAs) are used in various systems that use reconfigurable function. Conventional FPGAs have been developed by a transistor-level description for minimizing routing delay. Although FPGAs developed by the register transfer level (RTL) design methodology provide various benefits to the designers of a system-on-a-chip (SoC), they have not been realized. Therefore, the authors have advanced their development. They should be shown to operate in a practical throughput. For this purpose, circuits on them need to be designed and evaluated. In this paper, a ripple-carry adder (RCA) is designed on them and the throughput of the RCA is evaluated. The throughput shows that it is applicable to network processors. In addition, a wave-pipelined operation without changing the RCA reveals that the problem of routing delay in the FPGAs developed by the RTL methodology is mitigated.
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    A crossbar switch circuit design for reconfigurable wave-pipelined circuits
    (2014-01-01)
    Sato, Tomoaki
    ;
    Chivapreecha, Sorawat
    ;
    Moungnoul, Phichet
    This paper states crossbar switches which are used for the efficient design in reconfigurable wave-pipelined circuits. In the hardware- and host-based IPS (Intrusion Prevention System) which is used in mobile computing, reconfigurable circuits for intrusion detecting are implemented and their design requires techniques for highspeed and low-power operations. Wave-pipeline is a technique for realizing them. On the other hand, using it makes a problem that consumes a large amount of logic block in a conventional FPGA (Field-Programmable Gate Array). To solve this problem, the authors have developed a logic block for wave-pipelining. However, a crossbar switch for controlling the logic blocks to be used has not been developed. In this paper, the crossbar switches are developed in RTL (Register Transfer Level) and delay times, area and power are calculated.
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    Designing a Fine-Tuning Tool for Machine Learning with High-Speed and Low-Power Processing
    (2018-12-24)
    Sato, Tomoaki
    ;
    Chivapreecha, Sorawat
    ;
    Higuchi, Kohji
    ;
    Moungnoul, Phichet
    Machine learning is used in various fields. In order to broaden its further applications, it is necessary to use an architecture that operates faster and with lower-power consumption than conventional architecture. In this paper, as an architecture for that, it is proposed to use the ASIC-FPGA architecture proposed by the authors. In circuits on FPGAS, wave-pipeline techniques can be introduced for further high through put processing. In order to further improve the performance of wave-pipelines on the FPGAS, fine-Tuning should be executed. A fine-Tuning tool essential for realizing these is developed.
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    A detection method of web authentication problems for mobile devices corresponding to IEEE 802.11ac
    (2018-05-30)
    Sato, Tomoaki
    ;
    Chivapreecha, Sorawat
    ;
    Higuchi, Kohji
    ;
    Moungnoul, Phichet
    Improvement in the performance of mobile devices makes many opportunities to watch high resolution moving images using a public Wi-Fi LAN service. A web authentication may be required to specify the network user when accessing the public Wi-Fi LAN service. For some authentications, Google, Facebook and Twitter accounts are used. Although the use of these accounts provides convenience, it has serious problems. If the website for the authentication is a phishing site, the account may be abused. The reason is that it is difficult for many users to identify phishing sites. The identification using the CPU of a mobile device has a problem that it cannot deal with the throughput of IEEE 802.11ac. In this article, problems with web authentications used in public Wi-Fi LAN services are surveyed. Then, the authors propose a detection method of the problems that can deal with the throughput realized by IEEE 802.11ac and can process with low-power operations on mobile devices.