Chivapreecha, Sorawat
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Chivapreecha, Sorawat
Alternative Name
Chivapreecha, S.
Chivapreecha, Sorwat
Main Affiliation
Email
sorawat.ch@kmitl.ac.th
17 results
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Item type:Publication, A connection block implemented in the RTL design for delay time equalization of wave-pipelining(2015-01-01); Field-programmable gate arrays (FPGAS) which have many advantages are used in various devices. Use of the FPGAS is not only prototyping and verification of circuits but also an important part of the commercial products. A CPU of hardcore is required in the FPGAS. But it has a problem with the architecture of the CPU is limited. The method of solving these problems is developing a system on a chip (SoC) which is equipped with FPGAS and a customized CPU. From the view point of ease of design and shortening a design period, development techniques on a register-transfer level (RTL) using a standard cell library are essential. On the other hand, applying this method without using a design technique has a problem in terms of throughput. In this paper, a connection block for routing using wave-pipeline technique is proposed to solve the throughput problems. This block is evaluated, and it is shown that it is useful for wave pipeline operation. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Evaluation of Multi-Bit Input Logic Blocks in RTL-Designed FPGA Architecture: A Framework for FPGA and ASIC Integration(2025-01-01); This paper explores the evaluation and optimization of multi-bit input logic blocks (LBs) within RTL-designed FPGA architectures. Traditional FPGA designs face limitations in power consumption, delay, and area due to the constraints of reconfigurable circuits. The proposed architecture leverages RTL-level design capabilities to address these challenges and enables the co-design of FPGAs and ASICs. The authors evaluate the performance of 8-bit, 16-bit, and 32-bit input LBs in terms of delay, area, and synthesis feasibility. The results demonstrate that 8-bit input LBs achieve a delay of 0.68 ns with an area of 2202.48 μm<sup>2</sup>, outperforming multi-stage smaller LBs. Although 16-bit input LBs show potential for delay reduction, their synthesis demands significant time and results in a large area footprint, rendering them impractical. Synthesis of 32-bit input LBs was not feasible due to current tool limitations. These findings highlight the effectiveness of 8-bit input LBs for pattern matching tasks and emphasize the importance of application-specific optimization. The fixed routing feature of RTL-designed FPGAs facilitates the development of efficient, customizable designs tailored to specific workloads. This work contributes to the advancement of FPGA architectures, offering insights for future research on larger input LBs and their integration into high-performance applications. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, RCA on FPGAs designed by the RTL design methodology and wave-pipelined operation(2016-09-06); ; Higuchi, KohjiField-programmable gate arrays (FPGAs) are used in various systems that use reconfigurable function. Conventional FPGAs have been developed by a transistor-level description for minimizing routing delay. Although FPGAs developed by the register transfer level (RTL) design methodology provide various benefits to the designers of a system-on-a-chip (SoC), they have not been realized. Therefore, the authors have advanced their development. They should be shown to operate in a practical throughput. For this purpose, circuits on them need to be designed and evaluated. In this paper, a ripple-carry adder (RCA) is designed on them and the throughput of the RCA is evaluated. The throughput shows that it is applicable to network processors. In addition, a wave-pipelined operation without changing the RCA reveals that the problem of routing delay in the FPGAs developed by the RTL methodology is mitigated. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, A crossbar switch circuit design for reconfigurable wave-pipelined circuits(2014-01-01); This paper states crossbar switches which are used for the efficient design in reconfigurable wave-pipelined circuits. In the hardware- and host-based IPS (Intrusion Prevention System) which is used in mobile computing, reconfigurable circuits for intrusion detecting are implemented and their design requires techniques for highspeed and low-power operations. Wave-pipeline is a technique for realizing them. On the other hand, using it makes a problem that consumes a large amount of logic block in a conventional FPGA (Field-Programmable Gate Array). To solve this problem, the authors have developed a logic block for wave-pipelining. However, a crossbar switch for controlling the logic blocks to be used has not been developed. In this paper, the crossbar switches are developed in RTL (Register Transfer Level) and delay times, area and power are calculated. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Designing a Fine-Tuning Tool for Machine Learning with High-Speed and Low-Power Processing(2018-12-24); - Some of the metrics are blocked by yourconsent settings
Item type:Publication, A detection method of web authentication problems for mobile devices corresponding to IEEE 802.11ac(2018-05-30); - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Application-Optimized FPGAs Design Using RTL-Designed FPGAs Architectures(2025-01-01); RTL-Designed Field-Programmable Gate Arrays (FPGAs) can describe FPGA functionality using Hardware Description Languages (HDLs), which means they can be easily customized to configure the FPGA. In conventional FPGAs, switches are used for routing control, making it impossible to design them using HDLs. This study leverages the customizable nature of RTL-Designed FPGAs to explore the optimal configuration of FPGAs for packet processing in computer networks. It demonstrates that a 4-input Look-Up Table (LUT) is superior to a 3-input LUT in terms of throughput and reveals that, as the number of LUT inputs increases, having 5 routing paths is more optimal than 4. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Fine-tuning of wave-pipelines on FPGAs developed by the RTL design(2015-08-17); A wave-pipeline is a design technique for achieving high-speed and low-power operations also in field-programmable gate arrays (FPGAs). It realizes pipeline operations by adjusting delay times. Implementation of fine-tuning of wave-pipelines is possible to further increase the throughput. However, in the FPGA, it is not able to be executed by the restriction on the structure. This paper proposes a fine-tuning method for the FPGA developed by the register-transfer level (RTL) design. Although the RTL design of the FPGA has various advantages, it is required for a high-speed design for a routing delay which is larger than that of a conventional FPGA. The method is timing adjustment using a connection block with the RTL design. Results of analysis of the connection block show that the seven stages of the delay adjustment are possible in the block. In addition, the block can be used for rough-tuning of delay times. It is the area of less than half of the logic block. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Wiring control by RTL design for reconfigurable wave-pipelined circuits(2014-02-12); High-speed and low-power circuits of considering the development cycle for digital signal processing are very important in a mobile computing. The achievement of them on an FPGA (Field Programmable Gate Array) dominant in the point of shortening the development cycle. Nevertheless a reconfigurable device such as an FPGA for a power-aware design has not been developed. The authors have developed logic blocks for reconfigurable wave-pipelined circuits for the achievement of high-speed and low-power reconfigurable circuits. Wave-pipeline is one of a circuit design technique for high-speed processing and low-power consumption. They are very useful for the reduction in the resource on the FPGA. However, a wiring control to connect them have not been achieved. In this paper, the wiring control by RTL Design is developed. Its operation speeds are evaluated using 0.18 um CMOS technology. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Throughput of a Firewall Unit on FPGAS Developed by the RTL Design Methodology(2017-10-19); ; Higuchi, KohjiThe transmission speed of mobile communication systems for mobile and IoT (Internet of things) devices is getting faster. Advanced, high-speed and low-power processing on network packets are needed in these devices. To realize these performances in the devices, the authors have proposed FPGAS (field-programmable gate arrays) which are developed by the RTL (register-Transfer level) design methodology. As an application of the FPGAS for mobile communication systems, a firewall unit has been developed. However, the function of the firewall unit is only packet filtering. A function for deleting a packet passing through an unauthorized port has not been realized. In this paper, the authors design the firewall unit with the function of deleting the packet. The throughputs of the firewall unit are shown. Thus, it is clarified that high throughput can be accommodated.