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Fabrication of MEMS-based capacitive silicon microphone structure with staircase contour cavity using multi-film thickness mask
(2019-02-01)
Jantawong, Jirawat
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Atthi, Nithi
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Leepattarapongpan, Chana
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Srisuwan, Awirut
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Jeamsaksiri, Wutthinan
In this work, a silicon capacitive microphone structure with a three-dimensional staircase style contour cavity (S-CTC) is developed using a newly developed Multi Film Thickness photo lithography process. This newly developed Multi Film masking process overrides the conventional wisdom in which the staircase style cavity is formed using multiple exposures of mask and multiple etchings of silicon. With this newly developed photo lithographic technique, a Multi Film Thickness (MFT) mask is fabricated with varying chromium film thicknesses such as 0, 4, 14, and 114 nm thick. The mask was then evaluated to fabricate a microphone structure with a three-dimensional staircase style cavity. Once the mask was patterned onto a substrate, a single dry etching of silicon was carried out and a desired three-dimensional stair cavity pattern was achieved. Surprisingly, our results show that a capacitive sensor with an S-CTC structure has an increased absolute capacitance value by an average of 30% in comparison to a conventional box cavity (BC) structure. This may indeed improve SNR as we anticipated. The capacitance value changed from 2.2pf to 2.9pf for the same dimension of devices. This promising technology renders an opportunity to improve the next generation of ultra-low-pressure sensors for microphone applications.
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Fabrication of Contour Cavity Using Multi-Exposure Lithography for MEMS Capacitive Microphone
(2018-07-02)
Jantawong, Jirawat
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Atthi, Nithi
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Leepattarapongpan, Chana
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Jeamsaksiri, Wutthinan
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Austin, Anu
This paper presents a novel technique to optimize a capacitive pressure sensor with multi-exposure dose lithography. As part of achieving high signal to noise ratio (SNR) in microphone, a new design was implemented. The new design defies the conventional wisdom of parallel plate theory and implement a concept of contour cavity (backplate) to follows the diaphragm deflection. This 3-dimensional contour cavity (CC) is fabricated by multi-exposure dose lithography with single silicon etching process. The CC structure with different etched depth of 0.65, 1.15, and 1.57 micron were fabricated by multi-exposure dose of 92, 120, and 210 mJ/cm<sup>2</sup>on 5.0 micron thick photoresist and single step etching with CF<inf>4</inf>/O<inf>2</inf>plasma (Si/PR etch selectivity: 1.3). Due to this novel contour cavity design, polysilicon membrane with 0.8 micron thick and a diameter of 930 micron structure produces the capacitance value of 2.88 pF, which is 28.6% higher than that of conventional parallel plate capacitive sensor.
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Effects of Annealing Process on the Electrical Properties of MEMS Capacitive Microphone
(2018-07-02)
Jantawong, Jirawat
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Leepattarapongpan, Chana
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Chaowicharat, Ekalak
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Jeamsaksiri, Wutthinan
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Austin, Anu
In this paper, the effects of annealing temperature after pre-bonding device wafer and cover wafer during wafer fusion bonding process on the electrical properties of MEMS-based capacitive microphone with 0.53 μm thick poly-Si membrane were investigated. By the annealing in N2 ambient (14 SLM) at 900°C for 30 min, the device exhibited capacitance of 2.0 pF with pull-in voltage of 12 V. The significantly improvement of electrical properties is related to the reducing of residual stress in poly-Si membrane to near-zero level by using suitable annealing condition.
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The magnetotransistor for 2-axis magnetic field measurement in CMOS technology
(2015-08-17)
Leepattarapongpan, Chana
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Phetchakul, Toempong
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Pengpad, Puttapon
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Srihapat, Arckom
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Jeamsaksiri, Wutthinan
This paper presents a magnetotransistor for detecting magnetic field in vertical and lateral directions (B<inf>Y</inf> and B<inf>Z</inf>) by relying on the difference between base and collector currents (ΔI<inf>CB</inf>). It was designed and fabricated using CMOS fabrication technology. The device structure consisted of one emitter, 4 collectors and 4 bases. The experiment showed that, at 10 mA of biasing current, the B<inf>Y</inf> and B<inf>Z</inf> direction sensitivity to magnetic field within the range of 0 - 400 mT are 0.7 and 1.35 %/T, respectively. The sensitivity at emitter current 20mA are 0.55 and 0.7 %/T for vertical and lateral magnetic field directions, respectively. This research on the magnetotransistor produced magnetic sensors with small size, high performance with wide range of applications.
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The increase sensitivity of PNP-magnetotransistor in CMOS technology
(2015-02-02)
Leepattarapongpan, Chana
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Phetchakul, Toempong
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Pengpad, Puttapon
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Srihapat, Arckom
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Jeamsaksiri, Wutthinan
This paper presents improve sensitivity of pnp-magnetotransistor for detect vertical magnetic field response. The device structure consisted of one emitter, four collectors and four bases. The four collectors are separate to form four terminals. The same is true for the four bases. The experiment showed that, at 2 and 4mA of biasing current, magnetic field in B<inf>Z</inf> direction sensitivity within the range of 0-400 mT are 0.045 and 0.09 mV/mT in single mode. The sensitivity of merge mode are 0.15 and 0.3 mV/mT. The magnetic field response of merge mode shows 4-time increase of the magnetic field sensitivity comparative to single mode.
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A merged magnetotransistor for 3-axis magnetic field measurement based on carrier recombination-deflection effect
(2014-01-01)
Leepattarapongpan, Chana
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Phetchakul, Toempong
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Penpondee, Naritchaphan
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Pengpad, Puttapon
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Srihapat, Arckom
This article presents a novel magnetotransistor based on carrier recombination-deflection effect for detecting magnetic field in three dimensions (B<inf>X</inf>, B<inf>Y</inf>, and B<inf>Z</inf>) by relying on the difference between base and collector currents (I<inf>CB</inf>). This device used low biasing current. It was designed and fabricated using CMOS fabrication technology. The device structure consisted of one emitter, 4 collectors and 4 bases. All four collector terminals were connected with each other. The same was true for the four base terminals. LOCOS oxide was grown to surround the emitter area to limit lateral carrier loss, and therefore reducing the overall biasing current. The experiment showed that, at 0.2 mA of biasing current, the B <inf>X</inf>, B<inf>Y</inf> and B<inf>-Z</inf> direction sensitivity to magnetic field within the range of 0-400 mT are 2, 5 and 14.5%/T, respectively. This research on the merged magnetotransistor produced magnetic sensors with small size, high performance with wide range of applications. © 2014 Elsevier Ltd.
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A simulation of 3-axis magnetotransistor based on the carrier recombination - Deflection effect
(2014-01-01)
Phetchakul, Toempong
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Muangthong, Samudchad
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Leepattarapongpan, Chana
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Poyai, Amporn
This article presents 3 axis magnetotransistor based on the carrier recombination and deflection effect for detecting the magnetic field in B <inf>X</inf>, B<inf>Y</inf> and B<inf>Z</inf> direction. The structure composes of four magnetotransistors along with x-axis and y-axis that has a common emitter while all collectors and bases are independent. The output is in the form of difference current of collector and base ΔI<inf>CB</inf>. For vertical field detection, the magnetotransistor uses the carrier deflection of the deviation collector current and recombination base current as ΔI <inf>CB</inf>. For lateral field detection B<inf>X</inf> and B<inf>Y</inf> it uses a pair of transistors that emitter biased current perpendicular to magnetic field. The output response is the difference current between collector of one and the base current of the another of a pair transistors as ΔI <inf>C(1)B(3)</inf> and ΔI<inf>C(2)B(4)</inf> for B<inf>X</inf> and B <inf>y</inf>, respectively. The sensitivity at I<inf>E</inf> 5 mA, 0-1 T of B<inf>X</inf>, B<inf>Y</inf> and B<inf>Z</inf> direction are -0.0248 mA/T, -0.0248 mA/T and 0.0092 mA/T, respectively by TCAD Sentaurus simulation. © 2014 IEEE.
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The study of p-n and schottky junction for magnetodiode
(2012-01-01)
Phetchakul, Toempong
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Luanatikomkul, Wittaya
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Leepattarapongpan, Chana
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Chaowicharat, Ekalak
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Pengpad, Putapon
This paper presents the simulation model of Dual Magnetodiode and Dual Schottky Magnetodiode using Sentaurus TCAD to simulate the virtual structure of magneto device and apply Hall Effect to measure magnetic field response of the device. Firstly, we use the program to simulate the magnetodiode with p-type semiconductor and aluminum anode and measure electrical properties and magnetic field sensitivity. Simulation results show that sensitivity of Dual Schottky magnetodiode is higher than that of Dual magnetodiode.
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The low power 3D-magnetotransistor based on CMOS technology
(2011-12-01)
Leepattarapongpan, Chana
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Phetchakul, Toempong
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Penpondee, Naritchaphan
;
Pengpad, Puttapon
;
Srihapat, Arckom
This article presents a 3D magnetotransistor for detecting magnetic field in three dimensions (B <inf>X</inf>, B <inf>Y</inf>, and B <inf>Z</inf>) by relying on the difference between base and collector currents (ΔI <inf>CB</inf>). This device used low biasing current. It was designed and fabricated using CMOS fabrication technology. The device structure consisted of one emitter, 4 collectors and 4 bases. LOCOS oxide was grown to surround the emitter area to limit lateral carrier loss, and therefore reducing the overall biasing current. The experiment showed that, at 0.2 mA of biasing current, the BX, BY and BZ direction sensitivity to magnetic field within the range of 0 - 400 mT are 0.05, 0.07 and 0.145 mV/mT, respectively. © 2011 IEEE.
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The effect injection width and temperature-offset compensation of magnetotransistor
(2011-12-01)
Leepattarapongpan, Chana
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Phetchakul, Toempong
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Penpondee, Naritchaphan
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Pengpad, Puttapon
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Srihapat, Arckom
This paper presents effect of injection witdh on Magnetotransistor. Emitter area was confined by LOCOS and the injection window size was varied from 4, 5 to 10 microns. With bias current of 3 mA the window size 4 micron gives best sensitivity at 10mV/T. Measument linearity is 0.1 % full scale. voltage gain of 10 was used for minimizing temperature coefficient to be around 7.9 mV/°C measured from 25 to 125 °C. Temperature coefficient divided by sensitivity give us a relative temperature sensitivity of 7.9 % T/°C. Second magnetic sensor device has been used for temperature compensation. The second device was config as magnetic field immune then it was used as a temperature offset voltage reference. The added module reduces overall temperature sensitivy down to 0.3 % T/°C. © 2011 Published by Elsevier Ltd.

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