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Effect and Determination of Oxide Trapped Charge and Interface Trapped Charge Density of Threshold Voltage Shift in Irradiated MOSFET by Subthreshold Methodology
(2023-10-01)
Ruangphanit, Anucha
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Muanghlua, Rangson
;
Wongprasert, Yothin
This paper presents the effects and determination of oxide and interface trapped charge density of threshold voltage shift in irradiated MOSFET by subthreshold methodology. The designed dimension, channel width per channel length (W/L) is 20 µm/20 µm. The threshold voltage is extracted by a linear extrapolation methodology. The over all threshold voltage shifts are caused by oxide trapped charge and interface trapped charge. The subthreshold methodology determines the interface trapped charge. The<sup>60</sup>Co gamma-ray source was used for irradiation to a total dose of 10 kGy. The results showed that the threshold voltage shift is approximately-24 mV/kGy for NMOS and-27 mV/kGy for PMOS. The subthreshold swing shift is approximately 1.2 mV/dec.kGy for NMOS and 0.9 mV/dec.kGy for PMOS. The oxide trapped charge density N<inf>OT</inf> and interface trapped charge density N<inf>IT</inf> are found to be increased in NMOS and PMOS respectively. The ratio of ΔN<inf>OT</inf>/ΔN<inf>IT</inf> was approximately 2.2 times for NMOS and 2.8 times. Due to the structure, the channel of NMOS is a surface channel whereas the channel of PMOS is a buried channel. Finally, the effect of gamma irradiation on the PMOS was greater than the effect on NMOS observed from the change in threshold voltage and the ratio of ΔN<inf>OT</inf>/ΔN<inf>IT.</inf>.
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Uniformly Distributed RC Filters Based-on NMOS Transistor-Only
(2021-07-08)
Wachirarattanapornkul, Sorapong
This paper presents the construction of a passive uniformly distributed RC (hereafter as URC) device based-on NMOS transistor-only circuits with low phase shift characteristics and high-frequency support similar to the URC. The advantage of the proposed circuit has the variable the resistance-capacitance (RC) or time-constant () of the URC by the voltage control (VC). It to be used in selective-frequency cut-off on better than the normal passive URC, which can't be adjusted. In addition, the proposed circuit uses only a single voltage source to operate at only 2.5 V, resulting in low power consumption. The simulate by PSPICE simulation program was used on TSMC 0.25 um CMOS Technology compared with the passive lump URC to confirm the research results. And simulation results when made the proposed circuit into the low-pass filter and the high-pass filter circuit can be selective-frequency cut-off ranges at 40 kHz-1.6 GHz and 180 kHz-350 MHz by respective.
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Development a novel model of threshold voltage of NMOS with temperature dependence and narrow channel width
(2016-09-06)
Ruangphanit, A.
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Poyai, A.
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Muanghlua, R.
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Niemcharoen, S.
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Titiroongruang, W.
In paper, a development a novel model of threshold voltage of NMOS with temperature dependence and narrow channel width was presented. The models have been developed including the temperature affect of surface potentials, intrinsic carrier concentration and energy band gap. The threshold voltages were measured by the linear extrapolation methodology. The temperature dependence and the body-bias dependence of threshold voltage model of a big NMOS and a narrow channel width NMOS are proposed. The results show that, the measured threshold voltage compared with the development threshold voltage model was low level error.
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Implementation of the temperature and narrow channel dependence on threshold voltage model of NMOSFETs
(2014-01-01)
Ruangphanit, A.
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Sakuna, N.
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Niemcharoen
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Phinyo, B.
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Muanghlua, R.
In this paper, a new simplify mismatch of temperature and narrow channel dependence of threshold voltage of NMOS developed from spice level 3 and BSIM3 are proposed. The I<inf>DS</inf>-V<inf>GS</inf> in linear region was used with a different channel width. The parameters extraction procedure is based on the measurement of the transconductance characteristics of MOSFET in linear region. In this model, the temperature coefficient for threshold voltage and the body-bias coefficient of threshold voltage of a big MOSFET and a narrow channel width of MOSFET are determined. The results show that, the deviation of threshold voltage from the predicted model compared with the experimental data is less than 5%. © 2014 IEEE.
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The effects of temperature and device demension of MOSFETs on the DC characteristics of CMOS inverter
(2012-10-02)
Ruangphanit, A.
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Kiddee, K.
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Poyai, A.
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Wongprasert, Y.
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Niemcharoen, S.
The CMOS fabrication technology requires both n-channel (NMOS) and p-channel (PMOS) transistors be built on the same substrate. To ensure the reliability of the circuit performance over the temperature range, the circuits must be designed accommodate the basic variations parameters as a function of parameter. The temperature dependence of the MOSFET parameters as well as the small dimension effects on the dc characteristics of submicrometer CMOS inverters operated over the temperature range of 27- 125 degree Celsius are presented. The results show that the threshold voltage temperature coefficient (TCV) of both devices increased as the channel width decreased. PMOS has a larger affect more than NMOS because of a buried channel device. The Voltage Transfer Characteristics (VTC) of an inverter shows a symmetrical gate at WR is 2.0. However, the narrow channel effect, threshold voltage matching and ratio B <inf>R</inf> are key problem of CMOS inverter worked. Finally, these results will support the process engineer, circuit designer to improve device performance in the next fabrication. © 2012 IEEE.
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Extraction of mobility degradation, effective channel length and total series resistance of NMOS at elevated temperature
(2011-08-12)
Kiddee, Kunagone
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Ruangphanit, Anucha
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Niemcharoen, Surasak
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Atiwongsangthong, Narin
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Muanghlua, Rangson
This article describes the extraction of total series resistance, effective channel length and low field effective channel mobility degradation parameter at temperature in the range of 25°C-125°C of NMOS device. The relation of I<inf>DS</inf> and V<inf>GS</inf> in a linear region was used with a different of channel length. The procedure is based on the measurement of the transconductance characteristics of MOSFET in the linear region. The transconductance characteristics is determine for the several devices of difference drawn channel length. The results shows that, the effective channel length is increased in a range of 5×10<sup>-10</sup> m/°C. The low field mobility degradation parameter is decreased by the factor of 0.733. The total series resistance is increased in the range of 1.4 Ω-μm/°C. The errors between the predicted model and measured of I<inf>DS</inf>&V <inf>GS</inf> in linear region is approximately 3%. © 2011 IEEE.
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Substrate bias effects on Drain Induced Barrier Lowering (DIBL) in short channel NMOS FETs
(2009-07-01)
Ruangphanit, A.
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Phongphanchantra, N.
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Poyai, A.
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Hruanan, C.
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Muanghlua, R.
The substrate biasing characteristics of the Drain-Induced Barrier Lowering (DIBL) effects in short-channel NMOS devices with n+ polysilicon gate that fabricated at TMEC by 0.8 CMOS technology were presented. It was found that by increasing the substrate bias form -1 to -5V, DIBL in NMOS devices with mask channel length (L) from 0.6 to 3.0 micron shows the interesting feature. As the channel length decreased, the threshold voltage shift caused by DIBL first increased with increasing substrate bias and then decreased as the channel length decreased further for the range of L# 0.6 micron. But the DIBL increased with increasing substrate bias for the length of L between 0.8 and 1.2 micron. And almost neglected the substrate bias effect for the range of L > 1.2 micron. The substrate bias effect on subthreshold DIBL coefficient (ETAb) is approximately 3.5, 7.0, 8.0 and 0.7 mV/V for L of 0.8, 1.0, 1.2 and 3.0 micron respectively. Whereas the subthreshold DIBL coefficient (ETA0)is around 44, 10, 5 and 1.25 mV/V respectively. This change in DIBL with substrate bias for a short channel device can be explained as the transition of the surface DIBL effect to the subsurface DIBL effect and the onset of the punchthrough effect. Design considerations of the channel doping profile in short channel NMOS device for substrate bias based on improving the punchthrough and DIBL are also briefly discussed. © 2009, INSInet Publication.

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