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    Influence of graphene oxide concentration on IDES capacitive humidity sensor response behavior
    (2019-01-01)
    Pongampai, Satana
    ;
    Pengpad, Puttapon
    ;
    Meananeatra, Rattanawan
    ;
    Chaisriratanakul, Woraphan
    ;
    Thitirungraung, Wisut
    —Capacitive type humidity sensor was fabricated on CMOS technology by lithography process base on silicon p-substrate with Nitride passivation layer and designed on interdigitage electrodes (IDEs). This paper proposed the influence of various stock graphene oxide (GO) concentrations on humidity sensor responses behavior by drop coating method. The Raman spectroscopy is demonstrated for GO presence and scanning electron microscope (SEM) is exhibited the GO surface morphologies. The capacitance value is examined under different relative humidity (RH) ranges at 0.30% to 80% RH. The IDEs capacitive humidity sensor shows linear, polynomial and exponential responses behaviors for high, medium and low stock GO concentrations, respectively. The high stock GO concentration is significantly improved all dominant humidity sensor properties, especially the sensitivity at low RH (10%, 20%, 30% and 40% RH) which is improved up to 6683.65%, 2097.27%, 1984.91% and 1465.93%, respectively. Furthermore, it shows linear responses behavior by 0.991 for coefficient of determination of wide RH. Moreover, the IDEs capacitive humidity sensors are comparatively examined response/recovery times, hysteresis as well as repeatability. Finally, high stock GO concentration of humidity sensor is exhibited under various temperature operating ranges (20-50 degree Celsius). It clearly demonstrates for alternative applicability to use on humidity sensor applications.
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    Design high speed and low power hybrid full adder circuit
    (2018-12-24)
    Lueangsongchai, Sathaporn
    ;
    Tooprakai, Siraphop
    This paper presents 1-bit hybrid full adder cells circuit scheme that high speed and low power consumption. This Full adder cells circuit is designed utilization of XOR gate, XNOR gate, pass logic gate and transmission gate. Result of simulation by HSPICE program based on 16 nm CMOS technology with 0.9V power supply voltage and maximum frequency at 8GHz.
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    A comprehensive treatment of parametric effect in a silicon microring resonator
    (2016-05-18)
    Nawi, I. N.M.
    ;
    Ali, J.
    ;
    Yupapin, P. P.
    Silicon microring resonator provides a new platform to form the building block for all-optical circuits, where it could be integrated on a single chip as a passive or active components. Here, we report a comprehensive treatment of parametric effect in a symmetrical add/drop silicon microring resonator with 5 μm radius operating within telecom wavelength spectrum or C-band ranging from 1530 nm to 1565 nm. The power outputs of the system are analyzed by using transfer matrix method. The FSR and FWHM have been optimized. The results demonstrated here will pave the way towards the new on-chip and chip-to-chip architecture and structure for low power and high bandwidth applications especially for all-optical switch and optical modulator.
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    Soliton pulse induces TPA effect in a silicon MRR all-optical switch
    (2016-05-18)
    Nawi, I. N.M.
    ;
    Ali, J.
    ;
    Yupapin, P. P.
    One of the critical problems in achieving a real practical all-optical switching devices is the requirement for a strong material nonlinearity. A strong material nonlinearity is crucial in order to achieve a low switching power. However, silicon-based all-optical switches require extremely high switching power due to its relatively weak nonlinear optical properties. To overcome this limitation, we have designed an all-optical switch configuration based on silicon microring resonator structure and demonstrated the switching operation based on the nonlinear effects induced by a soliton pulse. The soliton pulse induces free-carrier concentration through two-photon absorption (TPA) effect and this leads to enhance the refractive index change and enhance the nonlinearity of the silicon. Thus, the silicon microring resonator alters the nonlinear phase shift which is required for switching.
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    CMOS differential difference voltage follower transconductance amplifier
    (2016-01-27)
    Kumngern, Montree
    This paper presents a new active building block for analog circuit applications called differential difference voltage follower transconductance amplifier. It consists of two parts: first part is the input that provides a differential difference voltage follower and second part is the transconductance amplifier that uses to convert differential difference input voltage to the output current. Hence, the electronic tuning capability of the proposed active building block can be obtained. The active building block is used to realize a universal biquadratic filter as an example application. Simulation results using 0.5 μm standard CMOS process are used to confirm the proposed active building block.
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    Defect distribution and yield analysis technique on silicon wafer
    (2014-01-01)
    Praepattarapisut, Warakorn
    ;
    Pengchan, Weera
    ;
    Phetchakul, Toempong
    ;
    Poyai, Amporn
    This paper presents the defect distribution and yield analysis on silicon wafer. The generation and recombination lifetime were the key parameters and obtained from the current- voltage and the capacitance-voltage of diode characteristics for forward bias. Then 3D contour maps were plotted as defect distribution and can be analyzed for the whole wafer which is useful for the yield analysis of the defects that were caused from fabrication process. © (2014) Trans Tech Publications, Switzerland.
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    CMOS precision full-wave and half-wave rectifier
    (2011-08-25)
    Virattiya, Athipong
    ;
    Knobnob, Boonying
    ;
    Kumngern, Montree
    This paper presents a new current-mode precision rectifier using CMOS technology. The system comprises a current comparator, current mirrors and diodes that can realize either a half-wave rectifier or a full-wave rectifier into a single system by appropriately adjusting the current gain of a current mirror. The proposed circuit offers low-voltage supply, low-power dissipation and wide bandwidth. The simulation results can be confirmed the operation and performance of the proposed rectifier. © 2011 IEEE.
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    Algorithmic ADC using current mode without DAC
    (2002-01-01)
    Tipsuwanporn, V.
    ;
    Numsomran, A.
    ;
    Chuchotsakunleot, W.
    ;
    Chuenarom, S.
    ;
    Maitreechit, S.
    This paper presents a principle of analog to digital conversion (ADC) based on a current mode circuit without DAC. For example, in this circuit the input value can be converted to a 4 bit output at each moment, and multiple output bit numbers by serial connection. In this current mode, the active current mirror and current comparators control the reference current by adjusting the W/L ratio. Its feasibility agrees with simulation results by the PSPICE program. The circuit design used a CMOS 0.5 μm process which is capable of converting 4 bits in 50 ns, with a power consumption of 0.127 mW, input current of 0-100 μA and single 3 V supply. From simulation testing, the conversion rate is faster than other methods using the same parameters.
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    ±1.5V high performance CMOS rail to rail voltage follower
    (2002-01-01)
    Kasemsuwan, V.
    ;
    Boonyaporn, P.
    ;
    Thanachayanont, A.
    A ±1.5 V high performance CMOS rail to rail voltage follower is presented. The circuit is based on the symmetrical class AB voltage follower and can operate under supply voltages of 1.5 V. The proposed circuit has power dissipation of 5.2 mW under quiescent condition and can drive ±1.25 V to 250 Ω load with a total harmonic distortion of less than 0.5 percent and cut-off frequency of 237 MHz. Although simple, the proposed circuit enables the output transistors to drive the load efficiently.
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    100-MHz CMOS direct digital synthesizer with 10-bit DAC
    (2002-01-01)
    Meenakarn, C.
    ;
    Thanachayanont, A.
    This paper describes the design and implementation of an integrated direct digital synthesizer with a 10-bit on-chip digital-to-analog converter using a 0.5-μm CMOS technology. The DDS chip operates at 100-MHz maximum clock frequency under 3.3-V supply voltage, with 32-bit frequency, 12-bit phase and 10-bit amplitude resolution. The chip provides sinusoidal, sawtooth, ramp, square and random waveforms with phase and frequency modulation, and power-down function, occupies 12-mm<sup>2</sup> die area, and dissipates 0.4 W at 100-MHz clock rate. At 25-MHz sinusoidal output, the measured worst-case spurious noise is -65 dBc and the phase noise is -119 dBc/Hz at 100-kHz frequency offset.