Pengchan, Weera
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Preferred name
Pengchan, Weera
Alternative Name
Pengchan, W.
Main Affiliation
Email
weera.pe@kmitl.ac.th
3 results
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Item type:Publication, Power loss analysis based on leakage currentin PN junctions(2013-10-04); ; Poyai, AmpornThis paper is proposed to analyze the power loss from leakage current in p-n junctions in case of non-uniform defects. The different geometry p-n junctions have been fabricated by a standard 0.8 micron CMOS technology. The diode fabricated by the ion implantation process with two different condition. The reverse current and voltage (I-V)characteristics at varied temperature of p-n junctions have been measured. The power loss coefficient can be extracted from the leakage current versus temperature. Form the derivative of leakage current with temperature, the power loss with prediction trend curve can be obtained. © (2013) Trans Tech Publications, Switzerland. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Extraction of defect in doping silicon wafer by analyzing the lifetime profile method(2008-01-01); ; Poyai, A.The total leakage current in silicon p-n junction diodes compatible with 0.8 μm CMOS technology is investigated. The generation lifetime is a key parameter for the leakage current, which can be obtained from the current-voltage (I-V) and the capacitance-voltage (C-V) characteristics. As will be shown, the electrically active defect from ion implantation process generated in p-n junction can be extracted from the generation current density. © 2008 Trans Tech Publications, Switzerland. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Defect distribution and yield analysis technique on silicon wafer(2014-01-01); ; Poyai, AmpornThis paper presents the defect distribution and yield analysis on silicon wafer. The generation and recombination lifetime were the key parameters and obtained from the current- voltage and the capacitance-voltage of diode characteristics for forward bias. Then 3D contour maps were plotted as defect distribution and can be analyzed for the whole wafer which is useful for the yield analysis of the defects that were caused from fabrication process. © (2014) Trans Tech Publications, Switzerland.