Wisetphanichkij, Sompong

Preferred name

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School of Engineering

sompong.wi@kmitl.ac.th

Now showing 1 - 10 of 15

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Minimal Realization Plus Current Output CC-based Biquad Circuit
(2024-06-01)
Wisetphanichkij, Sompong
;
Angkeaw, Krit
;
Sra-Ium, Napat
This paper presents a minimal design of a biquad circuit using only one plus current output type-II current conveyor (CCII), one differential voltage current conveyor (DVCC) and grounded passive components. The circuit enables the implementation of all 5 basic filter types: low-pass (LP), band-pass (BP), high-pass (HP), band-stop (BS) and all-pass (AP) by selecting and adding input and output currents with no component matching constraints. Moreover, the circuit parameters ω<inf>0</inf> and Q can be set simply by adjusting the circuit components. The proposed biquad circuit performance has very low sensitivity to circuit components due to its simple structure and a small number of devices (2 active and 4 grounded passive components). This allows the circuit to work at high frequencies. Non-ideal and parasitic effects are investigated and discussed. The performance of the proposed topology was evaluated through PSPICE simulator using the 0.18 μm CMOS technology from the Taiwan Semiconductor Manufacturing Company (TSMC).
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A low-voltage CMOS current squarer circuit
(2005-12-01)
Wisetphanichkij, Sompong
;
Singkrajom, Natcha
;
Kumngern, Montree
;
Dejhan, Kobchai
This paper presents a low-voltage current-mode CMOS squarer circuit. The low voltage operation can be achieved by the simple circuit design of the simple CMOS current mirrors and voltage shifting circuit. The realization method uses the MOS square-law technique in saturation region and require only V <inf>Th</inf>+2V<inf>DS</inf>. Simulation results show that the proposed circuit works well at supply voltage of 1V for a 0.5μm technology. © 2005 IEEE.
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Low voltage wide band inverting current feedback amplifier
(2004-12-01)
Wisetphanichkij, Sompong
;
Dejhan, Kobchai
This paper proposes a new design of low voltage wide band inverting current feedback amplifier. With the simple and small circuit, leads to high frequency response up to 2.5 GHz, with high gain and large input/output dynamic range up to ± 0.5V under ± 0.7V supply voltage. The simulation performed with MOSIS 0.5 micron technology and results the excellent performance, stabilize under large range ambient temperature. This circuit also well performs in digital application and suitable for mixed-signal processing.
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Linear Range Enhancement Circuit for LVDT based on Bipolar OTA with Relative Error Control
(2022-01-01)
Wisetphanichkij, Sompong
This paper proposes a Linear Range Enhancement Circuit for Linear Variable Differential Transformer (L VDT) which was by inverse hyperbolic tangent function implemented by bipolar type OTA. The proposed circuit requires only 2 OpAmps, a bipolar-type OTA and a small number of passive elements. Furthermore, the mathematical models were used in the analysis to determine the configuration methods of the circuit to improve the linearity range enhancement techniques under controlled maximum relative error (%). Two configuration methods of relative error are 0% at center with flat top and ripple top with specific maximum relative error. The Pspice simulation results show the efficiency of the proposed technique for widening the linear operating displacement of the transducer up to 30mm for LVDT (ks = 50 v/m, and kn = 0.2) for 1 % of maximum relative error.
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Multi-resolution image registration based on correlation technique
(2005-01-01)
Wisetphanichkij, Sompong
;
Dejhan, Kobchai
This paper proposed the new techniques of the multi-resolution image registration. The two images (reference and searching images), firstly, were prepared by decompose to multi-resolution images with discrete wavelet transform (DWT). Then the factional masks are created and convert to the binary masks base-on prior information. This efficiency mask-based algorithm operates in the coarse-to-fine resolution fashion on low-pass sub-band of decomposed image. Then the correlation performed at each resolution level to accomplish the registration problem © 2005 IEEE.
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A design of ternary Schmitt trigger circuit
(1999-12-01)
Angkaew, Krit
;
Wisetphanichkij, Sompong
;
Dejhan, Kobchai
;
Cheevasuvit, Fusak
;
Junnapiya, Somyot
This paper proposes a design of Schmitt trigger circuit with multi-level signal or ternary Schmitt trigger. The circuit operates on current mode with two-current comparator circuits by using positive feedback technique, the threshold current can be generated. And the last stage is V-I converter uses to produce and combine each hysteresis loop as the ternary Schmitt trigger operation. All results have been verified by simulating on PSpice based on ES2 technology model.
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A 1.1-V Low power true single-phase clock 2/3 prescaler
(2017-10-19)
Tooprakai, Siraphop
;
Wisetphanichkij, Sompong
;
Tudsorn, Apirak
This paper is proposed a low-power CMOS 2/3 prescaler using true single-phase technique on 45 nm CMOS technology with 1.1 V. The true-single-phase clock divider is used to achieve low power. The prescaler is capable of operating from 1 to 16 GHz. When operating at 1 GHz, it saves more power consumption compared to that of a conventional circuit and lowpower true single-phase clock CMOS 2/3 prescalers circuit operating in divide-by-2 mode and in divide-by-3 mode, respectively.
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Minimal Realization Plus Current Output CC-based Biquad Circuit
(2023-01-01)
Wisetphanichkij, Sompong
;
Angkeaw, Krit
;
Sra-Ium, Napat
This paper presents a minimal design of biquad circuit using only one plus current output type-II current conveyor (CCII), one differential voltage current conveyor (DVCC) and grounded passive components. The circuit enables all 5 basic filter types, low-pass (LP), band-pass (BP), high-pass (HP), band-stop (BS) and all-pass (AP) implementation by the selection and addition of the input and output currents with no component matching constraints. Moreover, the circuit parameters $\omega$0 and Q can be set simply by adjusting the circuit components. The proposed biquad circuit performance has very low sensitivity to circuit components due to its simple structure and small number of devices (2 active and 4 grounded passive components). This allows the circuit to work at high frequencies. The performance of the proposed topology was evaluated through PSPICE simulator using the 0. 1S$\mu$m CMOS technology from the Taiwan Semiconductor Manufacturing Company (TSMC).
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High-speed and low-power ECL circuits design based on BiCMOS technology
(1998-12-01)
Wisetphanichkij, Sompong
;
Dejhan, Kobchai
;
Cheevasuvit, Fusak
This paper proposes the high speed digital circuit design techniques in order to obtain the small circuit area and low power dissipation. The proposed techniques are a developed feedback controlled current source-active pull down-emitter coupled logic (FCCS-APD-ECL) and a current mirror biasing circuit of gated diode-active pull down-emitter coupled logic (GD-APD-ECL). The technique of FCCS-APD-ECL is used to obtain small circuit chip area and low power dissipation, the technique of GD-APD-ECL is used to obtain the high speed of the circuit. Both proposed circuits performances are carried out.
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Planar array waveguide auto-alignment based on adaptive evolution optimization method
(2005-12-01)
Wisetphanichkij, Sompong
;
Dejhan, Kobchai
;
Angkaew, Krit
;
Kornsuthathipkul, Kreangsak
The new active alignment technique was developed for planar lightwave circuit platform. The technique was successfully applied to the small spot-size laser diode align to 9um-diameter core size of the planar waveguide. This new auto-alignment procedure is designed which be based on an evolutionary optimization method. While the self-adaptive adjustment is created, it give the efficient alignment which can be obtained with the advantages of active alignment (low excess loss, good loss uniformity and high yield) and the time consuming is extremely reduced. The rough mesh-scanning (x-y axis) was initialized to the adaptive evolutionary search, and then the virtual cubic was created in searching space. The vertices and centre of cubic were searched. Then the virtual cubic will be moved until the center of virtual cubic has minimum excess loss. In case of the consecutive center of cubic is the same point, the size of cubic will be scaled in each dimension independently. The scaling factor will be self-selected and based on the prior information of alignment process to reach the global optimum point. This yields is fast and high repeatability alignment that suit for a large-volume manufacturing. © 2005 IEEE.

Wisetphanichkij, Sompong

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