Muanghlua, Rangson
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Muanghlua, Rangson
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Muanghlua, R.
Muanghlua, Rangsan
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rangson.mu@kmitl.ac.th
15 results
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Item type:Publication, The effects of geometrical capacitance components of LOCOS diode in VLSI(2019-03-01) ;Nissai, Itsariya ;Ruangphanit, Anucha; The effects of geometrical capacitance components of LOCal Oxidation of Silicon (LOCOS) diode in Very Large Scale Integrated circuit (VLSI) are proposed. For the correct circuit model simulation, the model of the device must be accurate and consistence with the SPICE models. The rectangular structure (L=400 μm, W=200 μm), the multi-fringe structure 1 (L=400 μm, W=4 μm, no. strips =50) and the multi-fringe structure 2 (L= S μm, W= Sμm, no. sample =1200) have been designed. These extraction methodologies show the area capacitance component, the peripheral capacitance component and the corner capacitance component at the field oxide side. The BSIM 3v3 junction capacitance models are proposed also. The comparison is made to check the accuracy of the parameter models. The results showed a low level error. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Investigation of Oxide and Interface Trapped Charge on Threshold Voltage Shift in Gamma Irradiated NMOSFET by Subthreshold Method(2021-04-01) ;Ruangphanit, AnuchaIn this paper, the oxide trapped charge density (NOT) and interface trapped charge density (NIT) on the threshold voltage shift with the total dose under gamma irradiation of NMOSFET are investigated. The subthreshold technique (mV/dec) is used to separate the irradiation induced threshold voltage shifts into voltage shifts due to the interface trapped charge. The linear extrapolation method is used to extract the threshold voltage from I{DS}-V{GS} curve at low VDS of typically 100 mV. The results showed that the threshold voltage was shifted from 0.69 V to 0.45 V, the threshold swing was increased from 95 to 107 mV/dec, the oxide charge and interface charge density were found to be increase almost by 1 order in magnitude for a total gamma dose of 10 kGy. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Measured and Extraction of Coupling Capacitive of Metal Interconnect Layers in VLSI(2018-07-02) ;Ruangphanit, Anucha ;Nissai, Itsariya ;Pedlub, RujipadThis paper presents the measurement and extraction of the capacitance for multilayer interconnections in VLSI. The capacitance of the capacitive coupling between interconnect is measured as a function of the varying frequency in order to develop a capacitance versus frequency curve. The multi-fringe structure of interconnect metal1 layer and interconnect metal2 layer \pmb{(\text{L}=400\mu \text{m}, \ \text{no}. \ \text{strip} =80)} with the total perimeter of capacitive coupling is approximately \pmb{3.16\times 10 {4}} \pmb{\mu} \mathbf{m} of value and the area is \pmb{2.8\times 10 {4}} \ \pmb{\mu\text{m} {2}} of value are tested respectively. The line width and line spacing ratio (W/S) of interconnect is varying from 0.9/0.6, 0.9/0.9, 0.9/1.05 and 0.9/1.2 with the measured frequency of 10kHz, 100kHz, 250kHz, 500kHz, IMHZ and 5 MHz are measured. The coupling of interconnect per unit length at various line spacing as a function of measured frequency of metal1 and metal2 are reported and discussed. The results show that the coupling capacitance per unit length \pmb{(\text{F}/\mu \text{m})} increases as the spacing between adjacent interconnect lines is deceased. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Structure and dielectric properties of Bi0.5K 0.5TiO3-SrTiO3 lead-free ceramics(2011-01-01) ;Ruangphanit, Anucha ;Phetnoi, Prapapim ;Niemcharoen, SurasakBismuth potassium titanate - strontium titanate (1-x)Bi<inf>0.5</inf>K <inf>0.5</inf>TiO<inf>3</inf>-(x)SrTiO<inf>3</inf> (BKT-ST) lead-free ceramics when x = 0-0.20 were synthesized by the solid state reaction method with normal sintering. The ferroelectric phase transition was studied by X-ray diffraction (XRD). All compositions showed a single phase perovskite structure with tetragonal symmetry at room temperature and the phase structure transformed from ferroelectric tetragonal - paraelectric cubic in the range of x ≥ 0.10. Dielectric study revealed that the dielectric relaxor behavior was induced with increasing ST and transition temperature (T<inf>m</inf> ε<inf>r max</inf>) of ST-doped BKT had a tendency to decrease with increasing ST. The Bi <inf>0.5</inf>K<inf>0.5</inf>TiO<inf>3</inf>-SrTiO<inf>3</inf> system was expected to be a new and promising candidate for lead-free capacitors. © (2011) Trans Tech Publications. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, The Effect of Gamma Irradiation on Threshold Voltage and Channel Mobility Degradation of NMOS(2018-07-02) ;Kerdpradist, Amonrat ;Ruangphanit, Anucha ;Titiroongruang, WisutThis paper presents the effect of Gamma Irradiated on threshold voltage, surface mobility and transconductance on N-channel MOSFET devices at a gate oxide thickness of 15 nanometers, which is fabricated at Thai Microelectronics Center by 0.8-micron CMOS technology. Then gamma irradiation (Co-60) at a total dose varied from 1 to 10 \mathbf{kGy}. By performing five rounds to observe changes in threshold voltage when the devices were exposed to gamma rays for measurement to extraction threshold Voltage (V<inf>TH</inf>) into the surface mobility (Uo) from I<inf>DS</inf>Vs V<inf>Gs</inf> curves in the saturation region. As a result, the threshold Voltage reduces at highest dose by approximately 38% compared with conventional N-channel MOSFET, for a parameter extraction in the level 3 model for MOSFET SPICE parameters is presented. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Effect and Determination of Oxide Trapped Charge and Interface Trapped Charge Density of Threshold Voltage Shift in Irradiated MOSFET by Subthreshold Methodology(2023-10-01) ;Ruangphanit, Anucha; This paper presents the effects and determination of oxide and interface trapped charge density of threshold voltage shift in irradiated MOSFET by subthreshold methodology. The designed dimension, channel width per channel length (W/L) is 20 µm/20 µm. The threshold voltage is extracted by a linear extrapolation methodology. The over all threshold voltage shifts are caused by oxide trapped charge and interface trapped charge. The subthreshold methodology determines the interface trapped charge. The<sup>60</sup>Co gamma-ray source was used for irradiation to a total dose of 10 kGy. The results showed that the threshold voltage shift is approximately-24 mV/kGy for NMOS and-27 mV/kGy for PMOS. The subthreshold swing shift is approximately 1.2 mV/dec.kGy for NMOS and 0.9 mV/dec.kGy for PMOS. The oxide trapped charge density N<inf>OT</inf> and interface trapped charge density N<inf>IT</inf> are found to be increased in NMOS and PMOS respectively. The ratio of ΔN<inf>OT</inf>/ΔN<inf>IT</inf> was approximately 2.2 times for NMOS and 2.8 times. Due to the structure, the channel of NMOS is a surface channel whereas the channel of PMOS is a buried channel. Finally, the effect of gamma irradiation on the PMOS was greater than the effect on NMOS observed from the change in threshold voltage and the ratio of ΔN<inf>OT</inf>/ΔN<inf>IT.</inf>. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Effects of Temperature and Channel Doping on the BSIM3 Threshold Voltage Model of NMOSFET form Substrate Bias Dependent Methodology(2016-01-01); ;Niemcharoen, Surasak ;Poyai, AmpornRuangphanit, AnuchaThe effects of channel doping and temperature dependence on the BSIM3 threshold voltage model of NMOSFET form substrate bias dependent methodology is proposed. The I<inf>DS</inf> -V<inf>GS</inf> in linear region with different substrate bias condition of a big size of NMOSFET was used. The threshold voltage parameters extraction procedure is based on the measurement of the transconductance characteristics of MOSFET in linear region. The electrical parameters γ, N<inf>CH</inf> and N<inf>SUB</inf> also the BSIM3 model parameter K<inf>1</inf> and K<inf>2</inf> at different channel implanted dose and different operating temperature are extracted. The model can be implemented in simulation tools with the error is less than 5%. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Preparation and properties of lead free bismuth sodium titanate-bismuth zinc titanate ceramics(2009-12-01); ;Niemcharoen, Surasak; ;Tungsitvisetkul, NattapongChinwaro, PimjanLead-free piezoelectric ceramics based on (1-x)Bi1/2Na1/2TiO3 - x Bi(Zn1/2 Ti1/2)O3 (x = 0.0, 0.02, 0.04, 0.06, 0.08, 0.10, 0.20, 0.30, 0.40, and 0.5) were obtained via solid-state processing techniques. The influence of BZT addition on BNT characteristics, sintering, microstructure and properties was investigated. A single perovskite phase with rhombohedral symmetry was obtained for Bi(Zn1/2Ti1/2)O3 substitutions of up to 10 mole%. A small amount of BZT was effective for improving both sintering behavior and dielectric properties of BNT ceramics. Optimized dielectric properties were obtained for samples with a maximum density of ρ = 98.3% for the composition, x = 0.1. Copyright © Taylor & Francis Group, LLC. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Extraction of mobility degradation, effective channel length and total series resistance of NMOS at elevated temperature(2011-08-12) ;Kiddee, Kunagone ;Ruangphanit, Anucha ;Niemcharoen, Surasak; This article describes the extraction of total series resistance, effective channel length and low field effective channel mobility degradation parameter at temperature in the range of 25°C-125°C of NMOS device. The relation of I<inf>DS</inf> and V<inf>GS</inf> in a linear region was used with a different of channel length. The procedure is based on the measurement of the transconductance characteristics of MOSFET in the linear region. The transconductance characteristics is determine for the several devices of difference drawn channel length. The results shows that, the effective channel length is increased in a range of 5×10<sup>-10</sup> m/°C. The low field mobility degradation parameter is decreased by the factor of 0.733. The total series resistance is increased in the range of 1.4 Ω-μm/°C. The errors between the predicted model and measured of I<inf>DS</inf>&V <inf>GS</inf> in linear region is approximately 3%. © 2011 IEEE. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Phase transitions and dielectric properties of lead-free Bi 0.5K0.5TiO3 - BaTiO3 piezoelectric ceramics(2011-08-12) ;Ruangphanit, Anucha ;Niemcharoen, Surasak; Lead free piezoelectric ceramics of (1-x)Bi<inf>0.5</inf>K <inf>0.5</inf>TiO<inf>3</inf> - xBaTiO<inf>3</inf> (BKT - BT) were fabricated by the solid state reaction method with normal sintering. The influence of BT addition on the crystal structure, phase transition and dielectric properties was investigated. The crystal structure and ferroelectric phase transition were studied by X-ray diffraction (XRD) and dielectric measurements. The complete solid solution of BKT - BT was observed for all compositions. In XRD results, all compositions showed a single phase perovskite structure with tetragonal symmetry at room temperature. With increasing BT content, the separation between diffraction peaks corresponded to increasing tetragonality. The phase transition temperature of ferroelectric tetragonal - paraelectric cubic (T <inf>C</inf>) decreased with increasing BT content. As the amount of BT concentration increased, the ceramic became denser, and almost no porosity was finally obtained. © 2011 IEEE.
