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Effect of Substrate Thickness on Horizontal Magnetoresistance
(2020-05-27)
Phetchakul, T.
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Chemthung, Y.
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Poyai, A.
This paper presents the effect of substrate thickness on horizontal magnetoresistance that detects the horizontal magnetic field perpendicular to bulk cross section area. The substrate thickness (T) concerns directly to the current density distribution and the effective depth (t) of current path corresponding to cross section area of current. The horizontal magnetoresistance depends on current distribution which concerns with substrate concentration, length, width and thickness of resistor. It changes by the effective depth of current path change by the unbalance between Lorentz's force and Hall electrical force in vertical direction. From this study, the sensitivity of device increases with the thickness of substrate up to critical substrate thickness and still constant for thickness greater than this critical value. The current distribution is limited when substrate thickness less than a critical value and fully distributes when the thickness is greater than this value. At the same constant current, the longer length of resistor shows the lower current density which needs the longer effective depth of current which causes the critical substrate thickness to be increased accordingly.
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Durable nitrate sensor by surface modification
(2016-11-25)
Chaisriratanakul, W.
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Bunjongpru, W.
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Jeamsaksiri, W.
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Srisuwan, A.
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Porntheeraphat, S.
This work presents the development of nitrate sensor based on Ion Sensitive Field Effect Transistor (ISFET) technology to achieve longer device's lifetime. This lifetime depended on the adhesion of PVC ion-selective membrane on the Si<inf>3</inf>N<inf>4</inf> sensing membrane of ISFET. The adhesion level directly affected the leaching of plasticizer. Such improvement utilized surface modification techniques by immersing the sensing membrane in the solution of 5% 3-mercaptopropyl-trimethoxysilane (MPTMS)/methanol. The modified surface was detected through the change of hydrophobicity and thickness of MPTMS using the contact angle measurement and ellipsometry techniques. The appropriate time for immersion was 18 h. The modified surface achieved the optimal hydrophobicity with contact angle of 100.32°. The presence of MPTMS film was confirmed by detecting the thiol-group using Fourier Transform Infrared (FTIR) spectrophotometry and Auger Electron Spectroscopy (AES). The PVC ion-selective membrane was then immobilized on the surface to create nitrate sensors with the following characteristics. The Nitrate-Nitrogen detection limit = 2.44 ppm with linear range from 5 to 60 ppm at sensitivity of 56 mV/dec. (R2 = 1). The response time was 90 s. Finally, this nitrate sensor could extend the total utilization lifetime from 8 to 17 weeks.
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Development a novel model of threshold voltage of NMOS with temperature dependence and narrow channel width
(2016-09-06)
Ruangphanit, A.
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Poyai, A.
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Muanghlua, R.
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Niemcharoen, S.
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Titiroongruang, W.
In paper, a development a novel model of threshold voltage of NMOS with temperature dependence and narrow channel width was presented. The models have been developed including the temperature affect of surface potentials, intrinsic carrier concentration and energy band gap. The threshold voltages were measured by the linear extrapolation methodology. The temperature dependence and the body-bias dependence of threshold voltage model of a big NMOS and a narrow channel width NMOS are proposed. The results show that, the measured threshold voltage compared with the development threshold voltage model was low level error.
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A new model for predicting the effect of temperature and devices dimension on threshold voltage of PMOS in VLSI
(2015-08-17)
Ruangphanit, A.
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Poyai, A.
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Sakuna, N.
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Niemcharoen, S.
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Muanghlua, R.
This paper presents a new model for predicting the effect of temperature and the devices dimension on the threshold voltage of PMOS. Temperature-dependent models have been developed including the temperature affect of surface potentials, intrinsic carrier concentration and energy band gap. The developed models have been used to study the temperature dependent and narrow channel width on the threshold voltage of PMOS. The new temperature coefficient for threshold voltage and the body-bias coefficient of threshold voltage of a big PMOS and a narrow channel width of MOSFET are proposed. The model can be implemented in simulation tools with the error is less than 3%.
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Yield analysis by poisson yield model based on the defect analysis with derivative method
(2014-01-01)
Praepattharapisut, W.
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Pengchan, W.
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Phetchakul, T.
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Poyai, A.
This paper presented the corresponding between the classical Poisson's yield equation prediction and wafer actual yield on the silicon wafer with 0.8 μm CMOS technology. The defect analysis with derivative method, current - voltage and capacitance-voltage of diode characteristic measurement, is used to define the defect in p-n junction on silicon wafer. The different sampling numbers of chips are used to calculate the yield. Finally the calculated data and actual would be compared and found that at sampling number is 25, the tolerance from actual yield is less than 2%. © 2014 IEEE.
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Contributing parameters for magnetoresistance effect of the new design on Hall plate structure
(2013-09-02)
Phetchakul, T.
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Taisettavatkul, P.
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Yamwong, W.
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Poyai, A.
This paper presents the parameters which contribute magnetoresistance effect of the new design on Hall plate structure when it is compared with series resistance structure. The new design is designed with rectangular aluminum ring surrounding on Hall plate. It creates zero Hall voltage area which the carriers move and deflect freely. The new and classical designs have percentage of magnetoresistance effect about 20% at doping concentration 2×10 15cm-3, temperature 300K at magnetic field 3 Tesla when classical one has metal space about 10 μm. The new design one is easier design than the classical series resistance and has no effect of metal space. Parameters which are used in this experiment are silicon and gallium arsenide at doping concentration 2×1014, 2×1015 and 2×1016 at temperature 200, 250 and 300K with Sentaurus TCAD program for simulation. The new design has the percentage of magnetoresistance effect much higher up to 906% over than the classical series resistance when it is designed with high mobility material, low doping concentration and low temperature. © 2013 IEEE.
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Temperature and devices dimension dependence on threshold voltage, the low field mobilty and the series parasitic resistance of PMOSFET
(2013-09-02)
Sakuna, N.
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Muanghlua, R.
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Niemcharoen, S.
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Ruangphanit, A.
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Poyai, A.
This paper presents the temperature and devices dimension dependence on the threshold voltage, low field mobility and series parasitic resistance of PMOS over operating temperature range of 27 °C to 125 °C. The relation of I<inf>DS</inf> and V<inf>GS</inf> in linear region was used with a different of channel length and channel width. The parameters extraction procedure is based on the measurement of the transconductance characteristics of MOSFET in linear region. The results show that, the temperature coefficient for threshold voltage is around 1.7mV/K approximately. The low field mobility degradation parameter is decreased by the factor of 0.68. The temperature coefficient of source-drain series resistance per unit channel width (R<inf>DSW</inf>) is approximately 16.7 ohm-um/K. These data are necessary not only should be compared with the results of NMOS but also should be used for the circuit designer to understanding well in the elevated operating temperatures. © 2013 IEEE.
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Very low drift and high sensitivity of nanocrystal-TiO 2 sensing membrane on pH-ISFET fabricated by CMOS compatible process
(2013-02-15)
Bunjongpru, W.
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Sungthong, A.
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Porntheeraphat, S.
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Rayanasukha, Y.
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Pankiew, A.
High sensitivity and very low drift rate pH sensors are successfully prepared by using nanocrystal-TiO <inf>2</inf> as sensing membrane of ion sensitive field effect transistor (ISFET) device fabricated via CMOS process. This paper describes the physical properties and sensing characteristics of the TiO <inf>2</inf> membrane prepared by annealing Ti and TiN thin films that deposited on SiO <inf>2</inf> /p-Si substrates through reactive DC magnetron sputtering system. The X-ray diffraction, scanning electron microscopy and Auger electron spectroscopy were used to investigate the structural and morphological features of deposited films after they had been subjected to annealing at various temperatures. The experimental results are interpreted in terms of the effects of amorphous-to-crystalline phase transition and subsequent oxidation of the annealed films. The electrolyte-insulator-semiconductor (EIS) device incorporating TiON membrane that had been obtained by annealing of TiN thin film at 850 °C exhibited a higher sensitivity (57 mV/pH), a higher linearity (1), a lower hysteresis voltage (1 mV in the pH cycle of 7 → 4 → 7 → 10 → 7), and a smaller drift rate (0.246 mV/h) than did those devices prepared at the other annealing temperatures. Furthermore, this pH-sensing device fabrication process is fully compatible with CMOS fabrication process technology. © 2012 Elsevier B.V. All rights reserved.
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The new design for magnetoresistance effect on hall plate structure
(2012-10-02)
Phetchakul, T.
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Taisettavatkul, P.
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Pengchan, W.
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Yamwong, W.
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Poyai, A.
This paper presents the new design which contributes to magnetoresistance effect on Hall plate by compared with series resistance structure by Sentaurus TCAD program. A new design creates zero Hall voltage area which the carriers move and deflect freely. The Hall plate structure is n-type silicon with 400 μm length, 100 μm width and 1 μm thickness. Both designs have percentage of magnetoresistance effect about 20% at doping concentration 2×10 15cm -3, temperature 300K at magnetic field 3 Tesla. A new design on Hall plate structure is easier than the classical series resistance and has no effect of metal space which is in series resistance structure. © 2012 IEEE.
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The effects of temperature and device demension of MOSFETs on the DC characteristics of CMOS inverter
(2012-10-02)
Ruangphanit, A.
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Kiddee, K.
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Poyai, A.
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Wongprasert, Y.
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Niemcharoen, S.
The CMOS fabrication technology requires both n-channel (NMOS) and p-channel (PMOS) transistors be built on the same substrate. To ensure the reliability of the circuit performance over the temperature range, the circuits must be designed accommodate the basic variations parameters as a function of parameter. The temperature dependence of the MOSFET parameters as well as the small dimension effects on the dc characteristics of submicrometer CMOS inverters operated over the temperature range of 27- 125 degree Celsius are presented. The results show that the threshold voltage temperature coefficient (TCV) of both devices increased as the channel width decreased. PMOS has a larger affect more than NMOS because of a buried channel device. The Voltage Transfer Characteristics (VTC) of an inverter shows a symmetrical gate at WR is 2.0. However, the narrow channel effect, threshold voltage matching and ratio B <inf>R</inf> are key problem of CMOS inverter worked. Finally, these results will support the process engineer, circuit designer to improve device performance in the next fabrication. © 2012 IEEE.

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