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Extraction of BSIM3V3 junction capacitance model of nMOSFET in VLSI: Devices,circuits and systems
(2018-07-02)
Ruangphanit, A.
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Pedlub, R.
;
Muanghlua, R.
An extraction methodology and modeling of BSIM3v3 junction capacitance of NMOSFET in VLSI is proposed. In this paper, the extraction can lead to an improved accuracy on p-n junction capacitance. This methodology can extract parasitic capacitance due to bottom area junction and side-wall capacitance components at the field oxide side and gate oxide side. The capacitance model parameters in BSIM3v3 are proposed also. The manual calculation was used for the extraction methodology. A comparison is made to checking the accuracy of the capacitance models. The results show that a good agreement was found.
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Test chip design and parameter extraction of parasitic capacitance of MOSFET in VLSI
(2017-10-19)
Ruangphanit, A.
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Pedlub, R.
;
Muanghlua, R.
This article describes test ship design and parameter extraction of parasitic capacitance of MOSFET in VLSI. The test structure for separating area and side-wall capacitance components of N+Psub junction and P+Nwell junction are used as testing devices. The BSIM3v3 models are proposed also. The results suggest that the correlation was found in 2% level. The manual calculation should be used for the benefit of extraction methodology. Finally, the overall data should be a data base of the design tool kit which hand out to the circuit designer in Multi Project Chip.
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Development a novel model of threshold voltage of NMOS with temperature dependence and narrow channel width
(2016-09-06)
Ruangphanit, A.
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Poyai, A.
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Muanghlua, R.
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Niemcharoen, S.
;
Titiroongruang, W.
In paper, a development a novel model of threshold voltage of NMOS with temperature dependence and narrow channel width was presented. The models have been developed including the temperature affect of surface potentials, intrinsic carrier concentration and energy band gap. The threshold voltages were measured by the linear extrapolation methodology. The temperature dependence and the body-bias dependence of threshold voltage model of a big NMOS and a narrow channel width NMOS are proposed. The results show that, the measured threshold voltage compared with the development threshold voltage model was low level error.
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A new model for predicting the effect of temperature and devices dimension on threshold voltage of PMOS in VLSI
(2015-08-17)
Ruangphanit, A.
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Poyai, A.
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Sakuna, N.
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Niemcharoen, S.
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Muanghlua, R.
This paper presents a new model for predicting the effect of temperature and the devices dimension on the threshold voltage of PMOS. Temperature-dependent models have been developed including the temperature affect of surface potentials, intrinsic carrier concentration and energy band gap. The developed models have been used to study the temperature dependent and narrow channel width on the threshold voltage of PMOS. The new temperature coefficient for threshold voltage and the body-bias coefficient of threshold voltage of a big PMOS and a narrow channel width of MOSFET are proposed. The model can be implemented in simulation tools with the error is less than 3%.
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Implementation of the temperature and narrow channel dependence on threshold voltage model of NMOSFETs
(2014-01-01)
Ruangphanit, A.
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Sakuna, N.
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Niemcharoen
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Phinyo, B.
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Muanghlua, R.
In this paper, a new simplify mismatch of temperature and narrow channel dependence of threshold voltage of NMOS developed from spice level 3 and BSIM3 are proposed. The I<inf>DS</inf>-V<inf>GS</inf> in linear region was used with a different channel width. The parameters extraction procedure is based on the measurement of the transconductance characteristics of MOSFET in linear region. In this model, the temperature coefficient for threshold voltage and the body-bias coefficient of threshold voltage of a big MOSFET and a narrow channel width of MOSFET are determined. The results show that, the deviation of threshold voltage from the predicted model compared with the experimental data is less than 5%. © 2014 IEEE.
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Temperature and devices dimension dependence on threshold voltage, the low field mobilty and the series parasitic resistance of PMOSFET
(2013-09-02)
Sakuna, N.
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Muanghlua, R.
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Niemcharoen, S.
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Ruangphanit, A.
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Poyai, A.
This paper presents the temperature and devices dimension dependence on the threshold voltage, low field mobility and series parasitic resistance of PMOS over operating temperature range of 27 °C to 125 °C. The relation of I<inf>DS</inf> and V<inf>GS</inf> in linear region was used with a different of channel length and channel width. The parameters extraction procedure is based on the measurement of the transconductance characteristics of MOSFET in linear region. The results show that, the temperature coefficient for threshold voltage is around 1.7mV/K approximately. The low field mobility degradation parameter is decreased by the factor of 0.68. The temperature coefficient of source-drain series resistance per unit channel width (R<inf>DSW</inf>) is approximately 16.7 ohm-um/K. These data are necessary not only should be compared with the results of NMOS but also should be used for the circuit designer to understanding well in the elevated operating temperatures. © 2013 IEEE.
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The effects of temperature and device demension of MOSFETs on the DC characteristics of CMOS inverter
(2012-10-02)
Ruangphanit, A.
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Kiddee, K.
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Poyai, A.
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Wongprasert, Y.
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Niemcharoen, S.
The CMOS fabrication technology requires both n-channel (NMOS) and p-channel (PMOS) transistors be built on the same substrate. To ensure the reliability of the circuit performance over the temperature range, the circuits must be designed accommodate the basic variations parameters as a function of parameter. The temperature dependence of the MOSFET parameters as well as the small dimension effects on the dc characteristics of submicrometer CMOS inverters operated over the temperature range of 27- 125 degree Celsius are presented. The results show that the threshold voltage temperature coefficient (TCV) of both devices increased as the channel width decreased. PMOS has a larger affect more than NMOS because of a buried channel device. The Voltage Transfer Characteristics (VTC) of an inverter shows a symmetrical gate at WR is 2.0. However, the narrow channel effect, threshold voltage matching and ratio B <inf>R</inf> are key problem of CMOS inverter worked. Finally, these results will support the process engineer, circuit designer to improve device performance in the next fabrication. © 2012 IEEE.
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Shot noise behavior of planar Mo/n-Si/Mo photodetector structure in avalanche mode
(2010-07-30)
Khunkhao, S.
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Umjaruan, C.
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Thaworn, A.
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Nuanloy, S.
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Niemcharoen, S.
Low-frequency (3 to 50 kHz) shot noise behavior of planar metal/semiconductor/metal photodetector (MSM-PD) structure operating under pre avalanching and avalanching conditions has been observed. The structure examined is Mo/n-Si/Mo structure with electrode separation of 20μm. In higher voltages applied, both device current and its photocurrent component showed a rapid increase at a critical bias voltage due to onset of avalanche multiplication. It was found that the associated shot noise factor Γ<sup>2</sup> varies in wide range from the order 0f 0.1 at pre-breakdown conditions to three orders of magnitude larger than unity corresponding to simple shot noise by avalanche multiplication. This result implies that the biasing condition for appropriate operation must be satisfied from the view point of signal-to noise ratio (S/N), when one operates this structure with high optical sensitivity. The value of noise factor obtained seems basically expressible by using existing theory with a little smaller exponent of multiplication factor.
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Multiplication of photocurrent in silicon planar metal-semiconductor-metal structures
(2009-10-22)
Khunkhao, S.
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Titiroongruang, W.
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Niemcharoen, S.
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Ruangphanit, A.
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Phongphanchanthra, N.
DC photocurrent gain properties of planar metal-semiconductor-metal (MSM) optical sensor structures on have been investigated experimentally. The test structure has two co-planar Mo/n-Si Schottky-barrier junctions on silicon of resistivity 9-12 Ω-cm and the electrode separation is 20 μm. The current-voltage (I-V) characteristics measurements under illumination in visible range showed a rapid increase in photocurrent at higher biases examined. From the temperature, the dependence of I-V characteristics and noise measurements, such photocurrent increase was ascribes to avalanche multiplication of carriers photogenerated in the Schottky junction reversed-biased. From low-frequency (10-50kHz) signal measurements, it was found that multiplication factor larger than 100 at 10kHz and 30 at 50kHz was achieved. ©2009 IEEE.
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Substrate bias effects on Drain Induced Barrier Lowering (DIBL) in short channel NMOS FETs
(2009-07-01)
Ruangphanit, A.
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Phongphanchantra, N.
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Poyai, A.
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Hruanan, C.
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Muanghlua, R.
The substrate biasing characteristics of the Drain-Induced Barrier Lowering (DIBL) effects in short-channel NMOS devices with n+ polysilicon gate that fabricated at TMEC by 0.8 CMOS technology were presented. It was found that by increasing the substrate bias form -1 to -5V, DIBL in NMOS devices with mask channel length (L) from 0.6 to 3.0 micron shows the interesting feature. As the channel length decreased, the threshold voltage shift caused by DIBL first increased with increasing substrate bias and then decreased as the channel length decreased further for the range of L# 0.6 micron. But the DIBL increased with increasing substrate bias for the length of L between 0.8 and 1.2 micron. And almost neglected the substrate bias effect for the range of L > 1.2 micron. The substrate bias effect on subthreshold DIBL coefficient (ETAb) is approximately 3.5, 7.0, 8.0 and 0.7 mV/V for L of 0.8, 1.0, 1.2 and 3.0 micron respectively. Whereas the subthreshold DIBL coefficient (ETA0)is around 44, 10, 5 and 1.25 mV/V respectively. This change in DIBL with substrate bias for a short channel device can be explained as the transition of the surface DIBL effect to the subsurface DIBL effect and the onset of the punchthrough effect. Design considerations of the channel doping profile in short channel NMOS device for substrate bias based on improving the punchthrough and DIBL are also briefly discussed. © 2009, INSInet Publication.

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