Pengchan, Weera
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Pengchan, Weera
Alternative Name
Pengchan, W.
Main Affiliation
Email
weera.pe@kmitl.ac.th
12 results
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Item type:Publication, The defects analysis in CMOS fabrication by arrhenius activation energy technique(2011-10-04); ; Poyai, AmpornLow power consumption device can be realized by low junction leakage current. This leakage current relates to the defects in the depletion region of p-n junction. Among variety process steps, implantation step may generate defects. Therefore, the implantation-induced defects have been studied from the activation energy which has been obtained from the leakage current of p-n junction. The different geometry p-n junctions have been fabricated by a standard CMOS technology. The current-voltage (I-V) and high frequency capacitance-voltage (C-V) characteristics of p-n junctions with temperature dependence have been measured. The electrically active defects from implantation process can be extracted from the junction generation current density versus temperature. Base on this analysis, it will be demonstrated that the implantation-induced defects have been found in p<sup>+</sup>-n-well more than in n<sup>+</sup>-p-substrate. Finally, the possible nature of the defect will be discussed. © 2011 IEEE. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Power loss analysis based on leakage currentin PN junctions(2013-10-04); ; Poyai, AmpornThis paper is proposed to analyze the power loss from leakage current in p-n junctions in case of non-uniform defects. The different geometry p-n junctions have been fabricated by a standard 0.8 micron CMOS technology. The diode fabricated by the ion implantation process with two different condition. The reverse current and voltage (I-V)characteristics at varied temperature of p-n junctions have been measured. The power loss coefficient can be extracted from the leakage current versus temperature. Form the derivative of leakage current with temperature, the power loss with prediction trend curve can be obtained. © (2013) Trans Tech Publications, Switzerland. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Effect of temperature on 16 nm n-FiNFET(2018-01-01)This research presents the effect of temperature that influence to the performance of 16 nm SOI n-FinFET structure. The structure has created with structure tool on GTS Framework. The transistor has 1 nanometer HfO<inf>2</inf> gate oxide with all metal contact and biased on Minimos-NT tool, with variation of temperatures from 300 K to 420 K with 30 K per step. The result found the decrease in saturation current, threshold voltage and mobility. The temperature brought electron and rose the density of electron as the potential from power supply that energized to the structure. They made mobility fall with them rising. The temperature makes a performance of FinFET structure. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, The local generation and recombination lifetime based on forward diode characteristics diagnostics(2013-01-01); ; Poyai, AmpornThis paper is proposed to extract the local carrier generation and recombination lifetime from forward characteristics of diode. The different geometry p-n junctions have been fabricated by a standard CMOS technology. Among a variety process steps, implantation step may generate defects. Therefore, the local implantation-induced defects have been studied from the defect activation energy, which has been obtained from the ratio of the local carrier generation and recombination lifetime. The forward current-voltage (I-V) and high frequency capacitance-voltage (C-V) characteristics of p-n junctions have been measured in order to obtain the local carrier generation and recombination lifetime. The calculated activation energy from this method gave reasonable values comparing with the ones obtained from the Arrhenius plot of the reverse current. © 2011 Elsevier B.V. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Yield analysis by poisson yield model based on the defect analysis with derivative method(2014-01-01); ; Poyai, A.This paper presented the corresponding between the classical Poisson's yield equation prediction and wafer actual yield on the silicon wafer with 0.8 μm CMOS technology. The defect analysis with derivative method, current - voltage and capacitance-voltage of diode characteristic measurement, is used to define the defect in p-n junction on silicon wafer. The different sampling numbers of chips are used to calculate the yield. Finally the calculated data and actual would be compared and found that at sampling number is 25, the tolerance from actual yield is less than 2%. © 2014 IEEE. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, The new design for magnetoresistance effect on hall plate structure(2012-10-02); ; - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Electrical characteristics of different gate geometry of FinFET(2016-01-01) - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Optical and electrical properties of diamond-like carbon thin film with deposition by ecr-cvd system(2019-01-01) - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Improved extraction of the local carrier generation lifetime from forward diode characteristics(2012-01-01); ; Poyai, AmpornThis paper is proposed to extract the local carrier generation lifetime from forward current-voltage (I-V) characteristics of p-n junctions in case of non-uniform defects. The different geometry p-n junctions have been fabricated by a standard CMOS technology. The forward I-V and high frequency capacitance-voltage (C-V) characteristics of p-n junctions have been measured. The recombination current density can be extracted from the area forward current density by subtracting with the area diffusion current density. Form the recombination current density, the local generation and recombination lifetime can be obtained. - Some of the metrics are blocked by yourconsent settings
Item type:Publication, Defect distribution and yield analysis technique on silicon wafer(2014-01-01); ; Poyai, AmpornThis paper presents the defect distribution and yield analysis on silicon wafer. The generation and recombination lifetime were the key parameters and obtained from the current- voltage and the capacitance-voltage of diode characteristics for forward bias. Then 3D contour maps were plotted as defect distribution and can be analyzed for the whole wafer which is useful for the yield analysis of the defects that were caused from fabrication process. © (2014) Trans Tech Publications, Switzerland.